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1. Pin descriptions
Pin No. Pin Name I/O Reset Short Description
Type Default
1 LOSCI AI / Low frequency crystal OSC input
2 LOSCO AO / Low frequency crystal OSC output
3 GND PWR / Digital signal ground
4 A15 O L Bit15 of ext. memory address bus
4(1) CLE O L Command latch enable of Nand type flash
5 AC’97RST- O H Reset to AC’97 block
5(1) ATA_RST- O H ATA device reset
6 A16 O L Bit16 of ext. memory address bus
6(1) ALE O L Address latch enable of Nand type flash
7 GIOB0 BI Z Bit0 of general purpose I/O port B
7(1) DAC_BCK O Z Ext. DAC bit clock output
8 A17 O L Bit17 of ext. memory address bus
8(1) ATAD8 BI L Bit8 of ATA device data bus
9 GIOB1 BI Z Bit1 of general purpose I/O port B
9(1) DAC_LR O Z Ext. DAC left/right channel output
10 A18 O L Bit18 of ext. memory address bus
10(1) ATAD9 BI L Bit9 of ATA device data bus
11 GIOB2 BI Z Bit2 of general purpose I/O port B
11(1) DAC_SDATA O Z Ext. DAC serial data output
12 A19 O L Bit19 of ext. memory address bus
12(1) ATAD10 BI L Bit10 of ATA device data bus
13 GIOB3 BI Z Bit3 of general purpose I/O port B
13(1) DAC_FS256 O Z Ext. DAC 256x over sampling clock
14 A20 O L Bit20 of ext. memory address bus
14(1) ATAD11 BI L Bit11 of ATA device data bus
15 GIOB4 BI Z Bit4 of general purpose I/O port B
15(1) AC’97BITCK O Z AC’97 codec bit clock
16 A21 O L Bit21 of ext. memory address bus
16(1) ATAD12 BI L Bit12 of ATA device data bus
17 GIOB5 BI Z Bit5 of general purpose I/O port B
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
U?
GIOG7
GIOG6
GIOG5
GIOD0
GIOD1
GIOG4
GIOD2
GIOD3
GIOD4
GIOD5
GIOG3
GIOD6
GIOD7
GIOE0
GIOE1
GIOE2
GIOG2
GIOE3
GIOE4
GIOE5
GIOE6
GIOE7
GIOG1
GIOG0
VCC
GND
VDD
GND
NMI-
MRD-
GIOF0
GIOF1
GIOF2
GIOF3
MWR-
A8
A7
A6
A5
A4
A3
A2
A1
A0
133 88
VCC GIOF4
134 87
A9 GIOF5
135 86
A10 GIOC5
136 85
A11 GIOF6
137 84
SIRQ- GIOC4
138 83
A12 GIOF7
139 82
A13 GIOC3
140 81
STANDBY- YDU
141 80
ZICEDO GIOC2
142 79
ZICEDI YSCLK/LP
143 78
ZICECK VCC
144 77
CE2- FRAME
145 76
TEST VDD
146 75
ZICERST- DISOFF
147 74
CE3- GIOC1
148 73
ZICEEN- XSCLK
149 72
CE4- GIOC0
A
T
J
2
0
0
1
P
1
7
6
150 71
RESET- CKOUT2
151 70
A14 GND
152 69
CE5- HOSCO
153 68
GND HOSCI
154 67
D0 AVSS
155 66
GIOA0 AVDD
156 65
D1 DCOP1
157 64
GIOA1 DCOP3
158 63
D2 DCOP2
159 62
GIOA2 VP2
160 61
D3 VDD2
161 60
D4 VP1
162 59
GIOA3 DCF1
163 58
D5 DCF2
164 57
A25/IFIN DCF3
165 56
VCC VBAT
166 55
D6 DCDIS
167 54
GIOA4 VL3
168 53
D7 VL2
169 52
CE0- VL1
170 51
GIOA5 VL0
171 50
CE1- VREFI
172 49
CE6- IBIAS
173 48
GIOA6 SEL
174 47
CE7- AVCC
175 46
GIOA7 X2
176 45
USBVBUS
AC97RST-
VDD X1
MICOUT
AOUTR
AOUTL
LOSCO
USBD+
USBD-
GIOB0
GIOB1
GIOB2
GIOB3
GIOB4
GIOB5
GIOB6
GIOB7
MICIN
AGND
LOSCI
VRDA
VRAD
VLAD
PVDD
PGND
PAOR
PAOL
VMIC
AGIC
PAIR
PAIL
GND
VCC
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
Y2
Y1
RA3930P176
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
ELECTRICAL CHARACTERISTIC
Notes 1. IvDD is a total power supply current for the 2.5 V power supply. IvDD is applied to the LOGIC and
PLL and OSC block.
Ivcc is a total power supply current for the 3.3 V power supply. Ivcc is applied to the USB,
IO, TP, and AD block.
VCC
0.6VCC 0.6VCC
All input pins Test Points
0.4VCC 0.4VCC
0V
VCC
All output pins Test Points
0.5VCC 0.5VCC
0V
VCC
tWRSL
RESET#
0V
(2) Initialization parameter
Parameter Symbol Condition MIN. MAX. Unit
32.768KHz
RESET#
tSS tOD
Hi-Z
I/O PINs Normal Operation
Sampling Point
t ACC
A[24:0]
t CE
CEn-/MRD-
t DS t DH
D[7:0](I)
Notes 1. MRD#, MWR# are called the command signals for the External System Bus Interface.
2. T (ns) = 1000 / fMCUCLK
MCUCLK 1 2 3
t XAS t XAH
A[24:0]
CEn-
MRD- t RXDS
t RXDH
D[7:0](I)
MWR- t XAH
t XAS
D[7:0](O)
t WXDS t WXDH
Bus Operation
(a) Instruction fetch cycle
MCU CLK
MRD#
CEn#
MCU CLK
MRD#
CEn#
MCU CLK
MWR#
CEn#
Key input delay time (from KEYOUT n↓) tKS Debounce time=2.5ms 0 µs
Key input hold time (from KEYOUT n↑) tKH Debounce time=2.5ms 0 µs
Remarks
1. KEYOUT(7:0) is multiplexed with GIOF(7:0); KEYIN(3:0) is multiplexed with GIOD(7:4); KEYIN(11:4) is
multiplexed with GIOE(7:0)
2. Keyscan Debouncing time is set thru Bit(2:0) of the MFP Configuration1 Register[0xB1h]
3. n = 0 to 7
KEYOUTn
(output) tKWAIT
tSCAN
KEYOUT(n+1)
(output)
Remark n=0 to 6
KEYOUT0 ss
(output)
KEYOUT7 ss
(output)
KEYOUTn
(output) tKH
tKS
KEYIN(7:0)
(input)
Remark n=0 to 7
1 0 0 0 1 1
1 0 1 1 0 0 1 1 0 1 0 1
Figure 7.2. Biphase-Mark Encoding
Sub-frame
bit 0 3 4 7 8 2728293031
MSB
LSB
Validity
User Data
Channel Status Data
Parity Bit
(10) D/A Converter Characteristics (TA =-10 to +70°C, VDD = 2.0 to 3.0 V, VCC = 2.7 to 3.6 V)
Parameter Symbol Condition MIN. TYP. MAX. Unit
Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions
Note Maximum number of days during which the product can be stored at a temperature of 25°C and a
relative humidity of 65% or less after dry-pack package is opened.
Caution Do not apply two or more different soldering methods to one chip (except for partial
heating method for terminal sections).
LQFP176: plastic low profile quad flat package; 176 leads; body 24 x 24 x 1.4 mm SOT506-1
y
X
132 89
133 88
ZE
E HE (A 3)
A A2 A1
θ
wM
Lp
bp L
detail X
pin 1 index
176 45
1 44
wM ZD v M A
e bp
D B
HD v M B
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
00-01-19
SOT506-1 136E25 MS-026
00-02-01