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spatan 33

spatan 33

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Published by: gengyuan on Jul 28, 2010
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DS312 (v3.8) August 26, 2009
1
 © 2005–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other coun-tries. All other trademarks are the property of their respective owners.
IntroductionFeaturesArchitectural OverviewPackage MarkingOrdering Information
Input/Output Blocks (IOBs)-Overview-SelectIOSignal StandardsConfigurable Logic Block (CLB)Block RAMDedicated MultipliersDigital Clock Manager (DCM)Clock NetworkConfigurationPowering Spartan®-3E FPGAsProduction Stepping
DC Electrical Characteristics-Absolute Maximum Ratings-Supply Voltage Specifications-Recommended Operating Conditions-DC CharacteristicsSwitching Characteristics-I/O Timing-SLICE Timing-DCM Timing-Block RAM Timing-Multiplier Timing-Configuration and JTAG Timing
Pin DescriptionsPackage OverviewPinout TablesFootprint Diagrams
0
Spartan-3E FPGA Family:Data Sheet
DS312 (v3.8) August 26, 2009
00
Product Specification
R
 
Spartan-3E FPGA Family: Data Sheet
2
DS312 (v3.8) August 26, 2009
Product Specification
R
 
DS312-1 (v3.8) August 26, 2009
3
Product Specification
 © 2005–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other coun-tries. All other trademarks are the property of their respective owners.
Introduction
The Spartan®-3E family of Field-Programmable GateArrays (FPGAs) is specifically designed to meet the needsof high volume, cost-sensitive consumer electronic applica-tions. The five-member family offers densities ranging from100,000 to 1.6 million system gates, as shown inTable1.The Spartan-3E family builds on the success of the earlierSpartan-3 family by increasing the amount of logic per I/O,significantly reducing the cost per logic cell. New featuresimprove system performance and reduce the cost of config-uration. These Spartan-3E FPGA enhancements, com-bined with advanced 90 nm process technology, delivermore functionality and bandwidth per dollar than was previ-ously possible, setting new standards in the programmablelogic industry.Because of their exceptionally low cost, Spartan-3E FPGAsare ideally suited to a wide range of consumer electronicsapplications, including broadband access, home network-ing, display/projection, and digital television equipment.The Spartan-3E family is a superior alternative to mask pro-grammed ASICs. FPGAs avoid the high initial cost, thelengthy development cycles, and the inherent inflexibility ofconventional ASICs. Also, FPGA programmability permitsdesign upgrades in the field with no hardware replacementnecessary, an impossibility with ASICs.
Features
Very low cost, high-performance logic solution forhigh-volume, consumer-oriented applicationsProven advanced 90-nanometer process technologyMulti-voltage, multi-standard SelectIO™ interface pins-Up to 376 I/O pins or 156 differential signal pairs-LVCMOS, LVTTL, HSTL, and SSTL single-endedsignal standards-3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling-622+ Mb/s data transfer rate per I/O-True LVDS, RSDS, mini-LVDS, differentialHSTL/SSTL differential I/O-Enhanced Double Data Rate (DDR) support-DDR SDRAM support up to 333 Mb/sAbundant, flexible logic resources-Densities up to 33,192 logic cells, includingoptional shift register or distributed RAM support-Efficient wide multiplexers, wide logic-Fast look-ahead carry logic-Enhanced 18 x 18 multipliers with optional pipeline-IEEE 1149.1/1532 JTAG programming/debug portHierarchical SelectRAM™ memory architecture-Up to 648 Kbits of fast block RAM-Up to 231 Kbits of efficient distributed RAMUp to eight Digital Clock Managers (DCMs)-Clock skew elimination (delay locked loop)-Frequency synthesis, multiplication, division-High-resolution phase shifting-Wide frequency range (5 MHz to over 300 MHz)Eight global clocks plus eight additional clocks pereach half of device, plus abundant low-skew routingConfiguration interface to industry-standard PROMs-Low-cost, space-saving SPI serial Flash PROM-x8 or x8/x16 parallel NOR Flash PROM-Low-cost Xilinx® Platform Flashwith JTAGComplete XilinxISE ® andWebPACK™ software
embedded processor cores
Fully compliant 32-/64-bit 33 MHzPCI support(66 MHz in some devices)Low-cost QFP and BGA packaging options-Common footprints support easy density migration-Pb-free packaging optionsXA Automotive versionavailable
8
Spartan-3E FPGA Family:Introduction and OrderingInformation
DS312-1 (v3.8) August 26, 2009
0
Product Specification
 
R
Table 1: 
Summary of Spartan-3E FPGA Attributes
DeviceSystemGatesEquivalentLogicCellsCLB Array(One CLB = Four Slices)DistributedRAM bits
(1)
Block RAMbits
(1)
DedicatedMultipliersDCMsMaximumUser I/OMaximumDifferentialI/O PairsRowsColumnsTotalCLBsTotalSlices
XC3S100E100K2,160221624096015K72K4210840XC3S250E250K5,50834266122,44838K216K12417268XC3S500E500K10,47646341,1644,65673K360K20423292XC3S1200E1200K19,51260462,1688,672136K504K288304124XC3S1600E1600K33,19276583,68814,752231K648K368376156
Notes:
1.
By convention, one Kb is equivalent to 1,024 bits.

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