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Microprocessor 8088/8086
What is a Computer?
Memory I/O
Processor
Data Bus
Address Bus
Control Bus
• CPU Registers
– special memory locations constructed
from flip-flops and implemented on-chip
– e.g., accumulator, count register, flag
register
• Arithmetic and Logic Unit (ALU)
– ALU is where most of the action take
place inside the CPU
Generate Generate
Address Address Address Unit
1 2
A19
Address Bus provides a memory Address Bus
address to system memory and
I/O address to system I/O devices A0
• Logical Memory
– 80x86 supports byte addressable memory
– byte (8 bits) is a basic memory unit
– e.g., when you specify address 24 in memory, you get the
entire eight bits
– when the microprocessors address a 16-bit word of
memory, two consecutive bytes are accessed
• Physical Memory
– The physical memories of 80x86 family differ in width
• e.g., 8088 memory is 8 bits wide,
• 8086, 80286 memory is 16 bits wide, and
• 80386dx, 80486 memory is 32 bits wide
– for programming there is no difference in memory
width, because the logical memory is always 8-bit
wide
– memory is organized in memory banks
• a memory bank is an 8-bit wide section of the memory
• e.g., the 16-bit microprocessors contain two memory banks
to form 16-bit wide section of memory that is addressed as
bytes or words
FFFFFD FFFFFC
FFFFFB FFFFFA
8 bits
8 bits
000005 000004
000003 000002
000001 000000
D15 - D8 D7- D0
• Text
– Letters and characters (7-bit ASCII
standard), e.g., 'A'=65=0x41
– Extended ASCII (8-bit) allows for
extra 128 graphics/symbols)
– Collection of characters = Strings
– Collection of Strings = Documents
• Programs
– Commands (MOV, JMP, AND, OR, NOT)
– Collections of commands = subroutines
– Collection of subroutines = programs
• Floating point numbers (covered later)
• Images (GIF, TIF, JPG, BMP)
• Video (MPEG, QuickTime, AVI)
• Audio (voice, music)
Note:
32 bit registers are
not available on
8086, 8088, 80286
• General-Purpose Registers
– AX (accumulator) often holds the
temporary result after an arithmetic and
logic operation
– BX (base) often holds the base (offset)
address of data located in the memory
•SI :來源索引暫存器。
DI :目的索引暫存器。
•SP: 堆疊指標暫存器。
•BP: 基底指標暫存器。
–SP 是堆疊指標,當使用 push 指令
時, sp 會加 2 ,而執行 pop 時 sp 會減 2 。
–BP 是可間接定址的暫存器,不過通常用於
堆疊段,如 mov ax,ss:[bp] 。
•註 :mov ax,ss:[bp] 中的 ss 為區段
( 或稱節段 ) 暫存器,若省略時,則會
取 ds 段的資料。
– DF :方向旗標。 IF :中斷旗標。
– TF :單步旗標。
•程式區段 CS : 如 IP 所執行位址都是 CS 程式
區段的內容。
•資料區段 DS : 如 mov ax,[bx] 間接定址法所
指都是資料段的資料。
•額外區段 ES : 如 mov ax,es:[di] 利用間接定
址法取其他區段記憶體資料時。
•堆疊區段 SS : 如 SP 堆疊資料,都是指在堆疊
段的。
•額外區段 FS :新增區段暫存器。
•額外區段 GS :新增區段暫存器。
Object Segment
Offset
Instruction CS
IP
Program data item DS
Explicit, BX,SI, or DI
Working storage item SS
SP or BP
Member of character sequence ES
DI
Embedded System Course
Real Mode Memory
Addressing (cont.)
• Generation of 20-bit linear address from a
segment:offset address
• in the real mode, each segment register (16
bits) is internally appended with a 0h on its
rightmost end (i.e., the segment is shifted
left by 4 bits)
• The segment and the offset are
then added to form 20-bit memory
address.
• Interrupts
– Notifies the CPU when an event has
occurred
• Timer [update clock] , serial I/O [input data],
Parallel I/O [ready]
• Network adapter [packet arrived]