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TMS320C6713B Digital Signal Processor

TMS320C6713B Digital Signal Processor

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TMS320C6713BFLOATINGPOINTDIGITALSIGNALPROCESSOR
SPRS294B − OCTOBER 2005 − REVISED JUNE 2006
1
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
D
Highest-Performance Floating-Point DigitalSignal Processor (DSP): TMS320C6713BEight 32-Bit Instructions/Cycle32/64-Bit Data Word300-, 225-, 200-MHz (GDP and ZDP), and225-, 200-, 167-MHz (PYP) Clock Rates3.3-, 4.4-, 5-, 6-Instruction Cycle Times2400/1800, 1800/1350, 1600/1200, and1336/1000 MIPS/MFLOPSRich Peripheral Set, Optimized for AudioHighly Optimized C/C++ CompilerExtended Temperature Devices Available
D
Advanced Very Long Instruction Word(VLIW) TMS320C67x
DSP CoreEight Independent Functional Units:2 ALUs (Fixed-Point)4 ALUs (Floating-/Fixed-Point)2 Multipliers (Floating-/Fixed-Point)Load-Store Architecture With 32 32-BitGeneral-Purpose RegistersInstruction Packing Reduces Code SizeAll Instructions Conditional
D
Instruction Set FeaturesNative Instructions for IEEE 754Single- and Double-PrecisionByte-Addressable (8-, 16-, 32-Bit Data)8-Bit Overflow ProtectionSaturation; Bit-Field Extract, Set, Clear;Bit-Counting; Normalization
D
L1/L2 Memory Architecture4K-Byte L1P Program Cache(Direct-Mapped)4K-Byte L1D Data Cache (2-Way)256K-Byte L2 Memory Total: 64K-ByteL2 Unified Cache/Mapped RAM, and192K-Byte Additional L2 Mapped RAM
D
Device ConfigurationBoot Mode: HPI, 8-, 16-, 32-Bit ROM BootEndianness: Little Endian, Big Endian
D
32-Bit External Memory Interface (EMIF)Glueless Interface to SRAM, EPROM,Flash, SBSRAM, and SDRAM512M-Byte Total Addressable ExternalMemory Space
D
Enhanced Direct-Memory-Access (EDMA)Controller (16 Independent Channels)
D
16-Bit Host-Port Interface (HPI)
D
Two McASPsTwo Independent Clock Zones Each(1 TX and 1 RX)Eight Serial Data Pins Per Port:Individually Assignable to any of theClock ZonesEach Clock Zone Includes:Programmable Clock GeneratorProgrammable Frame Sync GeneratorTDM Streams From 2-32 Time SlotsSupport for Slot Size:8, 12, 16, 20, 24, 28, 32 BitsData Formatter for Bit ManipulationWide Variety of I2S and Similar BitStream FormatsIntegrated Digital Audio InterfaceTransmitter (DIT) Supports:S/PDIF, IEC60958-1, AES-3, CP-430FormatsUp to 16 transmit pinsEnhanced Channel Status/User DataExtensive Error Checking and Recovery
D
Two Inter-Integrated Circuit Bus (I
2
C Bus
)Multi-Master and Slave Interfaces
D
Two Multichannel Buffered Serial Ports:Serial-Peripheral-Interface (SPI)High-Speed TDM InterfaceAC97 Interface
D
Two 32-Bit General-Purpose Timers
D
Dedicated GPIO Module With 16 pins(External Interrupt Capable)
D
Flexible Phase-Locked-Loop (PLL) BasedClock Generator Module
D
IEEE-1149.1 (JTAG
)Boundary-Scan-Compatible
D
208-Pin PowerPAD
PQFP (PYP)
D
272-BGA Packages (GDP and ZDP)
D
0.13-
µ
m/6-Level Copper Metal ProcessCMOS Technology
D
3.3-V I/Os, 1.2
-V Internal (GDP/ZDP/ PYP)
D
3.3-V I/Os, 1.4-V Internal (GDP/ZDP) [300MHz]
 
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
2006, Texas Instruments IncorporatedTMS320C67x and PowerPAD are trademarks of Texas Instruments.I2C Bus is a trademark of Philips Electronics N.V. CorporationAll trademarks are the property of their respective owners.IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.These values are compatible with existing 1.26-V designs.
PRODUCTIONDATAinformationiscurrentasofpublicationdate.ProductsconformtospecificationsperthetermsofTexasInstrumentsstandardwarranty.Productionprocessingdoesnotnecessarilyincludetestingofallparameters.
 
TMS320C6713BFLOATINGPOINTDIGITALSIGNALPROCESSOR
SPRS294B − OCTOBER 2005 − REVISED JUNE 2006
2
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
Table of Contents
EMIF device speed95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EMIF big endian mode correctness97. . . . . . . . . . . . . . . .bootmode98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .reset98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .absolute maximum ratings over operating casetemperature range99. . . . . . . . . . . . . . . . . . . . . . . . . .recommended operating conditions99. . . . . . . . . . . . . . . .electrical characteristics over recommended ranges ofsupply voltage and operating case temperature100parameter measurement information101. . . . . . . . . . . . . .signal transition levels101. . . . . . . . . . . . . . . . . . . . . . . . . . .timing parameters and board routing analysis103. . . . . .input and output clocks105. . . . . . . . . . . . . . . . . . . . . . . . . .asynchronous memory timing108. . . . . . . . . . . . . . . . . . . .synchronous-burst memory timing111. . . . . . . . . . . . . . . . .  synchronous DRAM timing113. . . . . . . . . . . . . . . . . . . . . . .HOLD/HOLDA timing119. . . . . . . . . . . . . . . . . . . . . . . . . . .BUSREQ timing120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .reset timing121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .external interrupt timing123. . . . . . . . . . . . . . . . . . . . . . . . .multichannel audio serial port (McASP) timing124. . . . . .inter-integrated circuits (I2C) timing127. . . . . . . . . . . . . . .host-port interface timing129. . . . . . . . . . . . . . . . . . . . . . . .multichannel buffered serial port timing132. . . . . . . . . . . .timer timing142. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .general-purpose input/output (GPIO) port timing143. . . .JTAG test-port timing144. . . . . . . . . . . . . . . . . . . . . . . . . . .mechanical data145. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .revision history3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GDP and ZDP 272-Ball BGA package (bottom view)5. . . . .PYP PowerPAD
QFP package (top view)10. . . . . . . . . . . .description11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .device characteristics12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .functional block and CPU (DSP core) diagram13. . . . . . . . . .CPU (DSP core) description14. . . . . . . . . . . . . . . . . . . . . . . . .memory map summary16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .peripheral register descriptions18. . . . . . . . . . . . . . . . . . . . . . .signal groups description27. . . . . . . . . . . . . . . . . . . . . . . . . . . .device configurations32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .configuration examples40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .debugging considerations47. . . . . . . . . . . . . . . . . . . . . . . . . . .terminal functions48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .development support64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .device support65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .CPU CSR register description68. . . . . . . . . . . . . . . . . . . . . . . .cache configuration (CCFG) register description70. . . . . . . .interrupts and interrupt selector71. . . . . . . . . . . . . . . . . . . . . . .external interrupt sources73. . . . . . . . . . . . . . . . . . . . . . . . . . . .EDMA module and EDMA selector74. . . . . . . . . . . . . . . . . . . .PLL and PLL controller77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .multichannel audio serial port (McASP) peripherals84. . . . .I2C89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .general-purpose input/output (GPIO)90. . . . . . . . . . . . . . . . . .power-down mode logic91. . . . . . . . . . . . . . . . . . . . . . . . . . . . .power-supply sequencing93. . . . . . . . . . . . . . . . . . . . . . . . . . . .IEEE 1149.1 JTAG compatibility statement95. . . . . . . . . . . . .power-supply decoupling94. . . . . . . . . . . . . . . . . . . . . . . . . . . .
 
TMS320C6713BFLOATINGPOINTDIGITALSIGNALPROCESSOR
SPRS294B − OCTOBER 2005 − REVISED JUNE 2006
3
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
REVISION HISTORY
The TMS320C67
13B
device-specific documentation has been split from
TMS320C6713, TMS320C6713B Float- ing−Point Digital Signal Processors 
, literature number SPRS186K, into a separate Data Sheet, literature numberSPRS294. It also highlights technical changes made to SPRS294 to generate SPRS294A. These changes aremarked by “
[Revision A]
.”
Additionally
,
 
made changes to SPRS294A to generate SPRS294B. These changesare marked by
“[Revision B]
.
Both Revision A and B changes are noted in the Revision History table below.
Scope:
Updated information on McASP, McBSP and JTAG for clarification. Changed Pin Description for A12 andB11 (Revisions SPRS294 and SPRS294A). Updated Nomenclature figure by adding device−specific informationfor the ZDP package. TI Recommends for
new designs 
that the following pins be configured as such:
D
Pin A12 connected directly to CV
DD
(core power)
D
Pin B11 connected directly to V
ss
(ground)
PAGE(S)NO.ADDITIONS/CHANGES/DELETIONS
6Terminal Assignments for the 272-Ball GDP and ZDP Packages (in Order of Ball No.) table:Updated Signal Name for Ball No. A12Updated Signal Name for Ball No. B1110PYP PowerPAD QFP package (top view):Updated drawing32Device Configurations, device configurations at device reset section:Updated “For proper device operation...” paragraph
[Revision B]
33Device Configurations, Device Configurations Pins at Device Reset (HD[4:3], HD8, HD12, and CLKMODE0) section:Removed “CE1 width 32−bit” from Functional Description for “
00
” in HD[4:3](BOOTMODE) Configuration Pin33Device Configurations, Device Configurations Pins at Device Reset (HD[4:3], HD8, HD12, and CLKMODE0) section:Updated “All other HD pins...” footnote
[Revision B]
37Table 22 Peripheral Pin Selection Matrix:Updated/changed MCBSP0DIS (DEVCFG bit) from “
ACLKKO
” to “
ACLKXO
46Configuration Example F (1 McBSP + HPI + 1 McASP) figure:Updated
from 
McBSP1DIS = 1
to 
McBSP1DIS = 047Device Configurations, debugging considerations section:Updated “Internal pullup/pulldown resistors...” paragraph
[Revision B]
49Terminal Functions, Resets and Interrupts section:Updated IPU/IPD for RESET Signal Name
from 
“IPU”
to 
“−−”50Terminal Functions table, Host Port Interface section:Removed “CE1 width 32−bit” from Description for “
00
” in Bootmode HD[4:3]50Terminal Functions table, Host Port Interface section:Updated “Other HD pins...” paragraph
[Revision B]
55Terminal Functions, Timer 1 section:Updated Description for TINP1/AHCLKX0 Signal Name57Terminal Functions, Reserved for Test section:Updated Description for RSV Signal Name, 181 PYP, A12 GDP/ZDPUpdated Description for RSV Signal Name, 180 PYP, B11 GDP/ZDP

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