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Section 13

Section 13

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Published by: Jeremie on Aug 08, 2010
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CS 61C Spring 2010 TA: Michael Greenbaum Section 114/118 Week 13 Caches cs61c-tf@inst.berkeley.edu
notesoriginallybyMattJohnson
More Pipelining Topics!
 
Hazards:
Our pipelined execution doesn’t always go smoothly. There are threespecific types of conflicts that can arise: what are they?
Superscalar Hardware:
Some pipeline problems happen when we don’t haveenough hardware (e.g. “If only I had two dryers…”). Superscalar means addingthat redundant hardware for some instruction-level parallelism! Would that helplatency or throughput? Who decides what hardware is used when?
Out-of-Order Execution:
After instruction fetch, dispatch to a queue where theinstruction waits until input operands are available. Queue is not always FIFO!Results are queued too, and write-back order happens in the “original” instructionorder. Pretty complex! Low-end processors still do not use this paradigm due tothe silicon area that is required for its implementation… In this class, OoOEwould essentially refer to hardware doing the work of filling branch/load delayslots. The lecture slides show an instruction pausing in the middle of itsexecution.
Caches!
Conceptual Questions:
Why do we cache? What is the end result of our caching, in terms of capability?What are temporal and spatial locality? Give high level examples in software of when these occur.
Break up an address:
 
T
ag
I
ndex
O
ffset
 
Offset
: “column index” (O bits)
Index
: “row index” (i bits)
Tag
: “cache number” that the block/row* came from. (T bits) [*difference?]
Segmenting the address into TIO implies a geometrical structure (and size)on our cache. Draw memory with that same geometry!
CacheMemory
 
2
i+O
BytesofData!
2
O
columns2
i
rows
Tag,Valid,&Dirtybits
2
T
CacheImages
Tag=0Tag=1Tag=2
 
 
CS 61C Spring 2010 TA: Michael Greenbaum Section 114/118 Week 13 Caches cs61c-tf@inst.berkeley.edu
notesoriginallybyMattJohnson
 
Cache Vocab
:
Cache hit
 – found the right thing in the cache! Booyah!
Cache miss
– Nothing in the cache block we checked, so read frommemory and write to cache!
Cache miss, block replacement
– We found a block, but it had the wrongtag!
Cache Exercises!
C1: Fill this one in… Everything here is Direct-Mapped!
AddressBitsCacheSizeBlockSizeTag Bits IndexBitsOffsetBitsBits per Row16 4KB 4B16 16KB 8B32 8KB 8B32 32KB 16B32 64KB 16 12 4 14632 512KB 564 64B 1464 2048KB 1069
C2:
Assume 16 B of memory and an 8B direct-mapped cache with 2-byte blocks.Classify each of the following memory accesses as hit (H), miss (M), or miss withreplacement (R).a. 4b. 5c. 2d. 6e. 1f. 10g. 7h. 2

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