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Fault Diagnosis Algorithm for Analog ElectronicCircuits based on Node-Frequency Approach

S.P. Venu Madhava Raomadhavaraosp@gmail.comDr. N. Sarat Chandra Babu & Dr. K. Lal KishoreAbstract: In this paper we present a novel approach toanalog electronic circuits fault diagnosis based onselection of both nodes and frequency for the first timeas far as we know. Two fault isolation and localizationalgorithms are presented in this paper. The firstalgorithm selects nodes and frequencies which isolateall or desired number of faults. The second algorithm presented converts the fault dictionary contents into binary form. Importantly this helps in the automationof the fault diagnosis process.Keywords: Fault Dictionary, Fault Isolation Table,Binary dictionary, singletons.I. IntroductionAnalog Fault Diagnosis has been of immenseresearch interest for the past three decades andcontinues to sustain the same zeal even today. Themain challenges today in analog fault diagnosis are todesign universally accepted fault models, costeffective, faster and accurate diagnosis of faults.Importantly all this is desired even in the presence of inherent characteristics of analog circuits liketolerances, non linearity, in accessible test nodes etc.There are two categories of analog circuit faultdiagnosis: Simulation before test (SBT) andSimulation after test (SAT) [1]. The SBT approachinvolves the generation of fault dictionary bysimulating the circuit and then using patternrecognition to identify the faults. This is the most popular method adopted. In SAT approach sufficientmeasurements are needed to identify faulty parameters.In the SBT approach construction of fault dictionary isan efficient method. Different test measurements likenode voltages, current sources, branch currents,frequency measurements etc are used in theconstruction of fault dictionaries [2]. There are somealgorithms developed to find out testablemeasurements using numerical approach in [3] and [4].In [5] a new method in the construction of faultdictionary is proposed where a combination of sensitivity based and information channel basedapproaches are used. Also the construction of integer coded fault dictionary using Quasi-Hamming distanceis proposed in this paper. Heuristic methods usingevolutionary computation in combination with theFuzzy logic is presented in [6], the main purpose of such a combination is to generate an optimizedfrequency test set and also ambiguity sets are providedto avoid take care of tolerance effects. An SBT basedapproach is proposed in [7] where the fault dictionaryis constructed using test node voltages and the methodused to approximate is Section wise piecewise linear (SPLF) method. A procedure for the selection of testfrequencies is presented in [8]. This is based on theevaluation of algebraic indices and the inverse norm of a sensitivity matrix of the circuit under test. In [9], [10]and [11], fault diagnosis based on different types of neural networks has been proposed. In [12] knowledge base and fuzzy logic have been used in fault diagnosis.The knowledge base is developed in two ways, one bysimulations and the second is based on heuristicsymptoms observed by the operator. In [13] theambiguity sets are divided based on the lowest error probability in the construction of fault dictionaries is proposed. This paper used Monte Carlo techniques for sensitivity analysis. In [14] a fault threshold functionand a fault criterion have been proposed for the faultdiagnosis of circuits with tolerance. An algorithm is proposed in [15], which aims to reduce the size of thefault dictionary. In [16] and [17] different methods andalgorithms are used to reduce the size of the faultdictionaries. In [18] time slot specification basedapproach is used in analog fault diagnosis. For this built in current sensors and test point insertion is used.A sensitivity based approach using randomizedalgorithms is used to diagnose soft faults in [19].In[20] the algorithm proposed tries to find the minimumnumber of test point for maximum fault isolation. Thisapproach is based on information measure of the test

(IJCSIS) International Journal of Computer Science and Information Security,Vol. 8, No. 4, July 2010291http://sites.google.com/site/ijcsis/ISSN 1947-5500

points. The diagnosis proposed in this paper [21] is based on global sensitivity analysis method. Alsofuzzy logic is used to obtain the sensitivity curves. In[22] an efficient method is applied in the selection of test nodes. This is done by searching for the minimumentropy index based on the available test points. Anefficient graph based method is proposed in [23].Thismethod can be used to select optimum test pointselection and also can be sued to build DFT. EfficientInclusion methods and Exclusion methods are proposed in [24] to select or de select test nodes, inother words the faster selection of optimum test points.A novel multi frequency approach is proposed in [25]which drastically reduce the number of test frequenciesneeded to achieve maximum fault diagnosis. Thereduction achieved is better than any known methods.The method proposed in [26] consists of two parts.One is the creation of fault dictionary consisting of nominal and faulty states of the components andsecond is a novel fault detection and localizationalgorithm.This paper proposes a novel approach where both testnode and multi frequency techniques are used. Thisapproach is used to diagnose all the faults or thedesired number of faults.II Node-Frequency ApproachIn the analog fault diagnosis the prominent methodsused are multi node or multi frequency measurements.The research so far has been on developing methods tofind out optimum number of test nodes or testfrequencies that can identify the desired faults. This insome cases leads to more number of measurements being made thus drastically increasing the size of thedictionary.In this paper we have taken basically nodal analysisand then a choice of test frequencies is made based on[27]. The proposed algorithm selects the nodes andfrequencies which isolate all or desired faults.In this paper two algorithms are presented. The firstalgorithm is for fault isolation and localization. Thesecond algorithm converts the integer coded faultdictionary into a binary dictionary which helps infaster fault isolation.The actual measurements of the CUT are noted downand these values are normalized if necessary. Fromthese values we form ambiguity sets. Now weconstruct another table called integer coded table usingambiguity sets. Then the original readings are replaced by integer numbers indicative of the ambiguity set towhich these values belong.The test frequency set is represented by f

to f

, where N is the number of frequencies chosen.The nodes are represented by n

to n

, where Prepresents the total number of nodes.The faults are represented by F

(nominal value) to F

,where N represents the total number of faults.

Algorithm 1:

Step 1:

Select the test frequency set (f

to f

Step 2:

Select the test nodes (n

to n

) which areaccessible for each frequency.

Step 3:

Note the actual readings of the circuit for thetest frequency set and nodes chosen in steps 1 and 2.

Step 4:

Form the integer coded dictionary using theambiguity sets.

Step 5:

Identify unique integer codes called singletonsfor each row i.e. for each of the nodes selected.

Step 6:

Identify the node (n

) which has maximumnumber of singletons for a frequency f

, where 1<K≤Pand 1<J≤M. Select this node-frequency (n

, f

) pair. If more than one node satisfies this condition, then go tostep 9.

Step 7:

If the number of singletons is equal to N+1,then go to step 12. If else go to next step 8.

Step 8:

Call Algorithm 2, to form binary dictionarywhich helps in identifying other nodes from theremaining (P-1) nodes belonging to the frequency f

,which can identify different faults. If all faults areisolated then go to step 12.

Step 9:

Find the total number of singletons for eachtest frequency. Then choose the node belonging to thefrequency which has the maximum number of singletons. If more than one frequency satisfies thiscondition choose any one of the nodes randomly.

Step 11:

If all the faults or desired number of faults arenot isolated, then repeat steps from 6 with the nexthighest number of singletons.

Step 12:

Stop

(IJCSIS) International Journal of Computer Science and Information Security,Vol. 8, No. 4, July 2010292http://sites.google.com/site/ijcsis/ISSN 1947-5500

Algorithm 2:

Step 1:

Replace all the singletons by the value ‘1’ andothers by ‘0’ in the integer coded table, resulting in a binary table.

Step 2:

If n

is the node chosen, then calculate (n

-n

), where 1<M≤P, thus forming another table called Node-Wise Fault Isolation table. This results in threevalues 0,-1 or 1. The value ‘0’ indicates that the faulthas been identified by both n

and n

or both thenodes did not isolate the fault, whereas ‘-1’ indicatesthat the fault has been isolated by only n

and ‘1’ is anindication that the fault has been identified by the nodeof interest i.e. n

. Therefore choose the node n

whichhas maximum number of 1’s.

Step 3:

Check the total number of faults isolated by thenodes n

and n

. If this sum is equal to P, then Stop,otherwise choose the node which has the next highestnumber of 1’s.

Step 4:

Repeat step 3 till the desired fault isolation isachieved or no further isolation is possible.

Step 5:

Return to Algorithm 1III. Integer coded dictionary based on ambiguity setsThe formation of the Integer coded dictionary based onambiguity sets is illustrated by an example in thissection. Assume that the actual readings of animaginary circuit under test are given in Table 1 below.Table 1: Actual readings of the imaginary CUT Node Nominal Fault-1 Fault-2 Fault-3 Node-1 1.22 0.33 0.78 0.34 Node-2 1.33 0 0.09 2.1 Node-3 1.45 0 0.99 2.5As seen from the Table 1 above, we see that for node -1 measurement, fault-1 and fault -3 have almostthe same value and thus belong to the same ambiguitygroup. Also these two values are the least among alland are assigned values ‘1’. The other values do not belong to any ambiguity group and are assigned values2 for fault-2 and 3 for nominal, based on the ascendingrange of the values. Using the same procedure for allthe remaining nodes, integer coded fault dictionary isformed and is shown in Table 2.Table 2: Integer Coded Fault Dictionary Node Nominal Fault-1 Fault-2 Fault-3 Node-1 3 1 2 1 Node-2 2 1 1 3 Node-3 3 1 2 4In the Table 2, we see that node-1 has 2 singletons,node-2 has 2 singletons and node 3 has 4 singletons.IV IllustrationThe circuit used here is a 2

order Butterworth HighPass Filter as shown in Fig. 1. The circuit has beensimulated using Tina Spice software.The faults chosen are taken as 50% increase or decrease in the component values. Thus CUT has beensimulated for these faults by changing the componentvalues by ±50%.

(IJCSIS) International Journal of Computer Science and Information Security,Vol. 8, No. 4, July 2010293http://sites.google.com/site/ijcsis/ISSN 1947-5500

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Fault Diagnosis Algorithm for Analog Electronic Circuits based on Node-Frequency Approach

In this paper we present a novel approach to analog electronic circuits fault diagnosis based on selection of both nodes and frequency for the first time as far as we know. Two fault isolation and localization… (More)

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