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404 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 56, NO. 5, MAY 2009

Modiﬁed Booth Multipliers With aRegular Partial Product Array

Shiann-Rong Kuang,

Member, IEEE

, Jiun-Ping Wang, and Cang-Yuan Guo

Abstract

—The conventional modiﬁed Booth encoding (MBE)generates an irregular partial product array because of the extrapartial product bit at the least signiﬁcant bit position of eachpartial product row. In this brief, a simple approach is proposed togenerate a regular partial product array with fewer partial prod-uct rows and negligible overhead, thereby lowering the complexityof partial product reduction and reducing the area, delay, andpower of MBE multipliers. The proposed approach can also beutilized to regularize the partial product array of posttruncatedMBE multipliers. Implementation results demonstrate that theproposed MBE multipliers with a regular partial product arrayreally achieve signiﬁcant improvement in area, delay, and powerconsumption when compared with conventional MBE multipliers.

Index Terms

—Modiﬁed booth, multiplier, partial products,posttruncated.

I. I

NTRODUCTION

E

NHANCING the processing performance and reducingthe power dissipation of the systems are the most im-portant design challenges for multimedia and digital signalprocessing (DSP) applications, in which multipliers frequentlydominate the system’s performance and power dissipation.Multiplication consists of three major steps: 1) recoding andgenerating partial products; 2) reducing the partial products bypartial product reduction schemes (e.g., Wallace tree [1]–[3])to two rows; and 3) adding the remaining two rows of partialproducts by using a carry-propagate adder (e.g., carry look-ahead adder) to obtain the ﬁnal product. There are already manytechniques developed in the past years for these three steps toimprove the performance of multipliers. In this brief, we willfocus on the ﬁrst step (i.e., partial product generation) to reducethe area, delay, and power consumption of multipliers.The partial products of multipliers are generally generatedby using two-input

AND

gates or a modiﬁed Booth encoding(MBE) algorithm [3]–[7]. The latter has widely been adoptedin parallel multipliers since it can reduce the number of partialproduct rows to be added by half, thus reducing the size andenhancing thespeed of the reduction tree. However, as shown inFig. 1(a), the conventional MBE algorithm generates

n/

2 + 1

partial product rows rather than

n/

2

due to the extra partialproduct bit (

neg

bit) at the least signiﬁcant bit position of

Manuscript received October 31, 2008; revised January 20, 2009. Currentversion published May 15, 2009. This work was supported in part by theNational Science Council, Taiwan, under Grant NSC 97-2220-E-110-006. Thispaper was recommended by Associate Editor A.-Y. Wu.The authors are with the Department of Computer Science and Engi-neering, National Sun Yat-sen University, Kaohsiung 80424, Taiwan (e-mail:srkuang@cse.nsysu.edu.tw).Digital Object Identiﬁer 10.1109/TCSII.2009.2019334Fig. 1. Conventional MBE partial product arrays for 8

×

8 multiplication.

each partial product row for negative encoding, leading to anirregular partial product array and a complex reduction tree.Some approaches [7], [8] have been proposed to generate moreregular partial product arrays, as shown in Fig. 1(b) and (c),for the MBE multipliers. Thus, the area, delay, and powerconsumption of the reduction tree, as well as the whole MBEmultiplier, can be reduced.In this brief, we extend the method proposed in [7] to gener-ate a parallelogram-shaped partial product array, which is moreregular than that of [7] and [8]. The proposed approach reducesthe partial product rows from

n/

2 + 1

to

n/

2

by incorporatingthe last

neg

bit into the sign extension bits of the ﬁrst partialproduct row, and almost no overhead is introduced to thepartialproductgenerator.Moreregularpartialproductarrayandfewer partial product rows result in a small and fast reductiontree, so that the area, delay, and power of MBE multiplierscan further be reduced. In addition, the proposed approachcan also be applied to regularize the partial product array of posttruncated MBE multipliers. Posttruncated multiplication,which generates the

2

n

-bit product and then rounds the productinto

n

bits, is desirable in many multimedia and DSP systemsdue to the ﬁxed register size and bus width inside the hard-ware. Experimental results show that the proposed general andposttruncated MBE multipliers with a regular partial productarray can achieve signiﬁcant improvement in area, delay, and

1549-7747/$25.00 © 2009 IEEE

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KUANG

et al.

: MODIFIED BOOTH MULTIPLIERS WITH A REGULAR PARTIAL PRODUCT ARRAY 405

TABLE IMBE T

ABLE

power consumption when compared with conventional MBEmultipliers.II. C

ONVENTIONAL

MBE M

ULTIPLIER

Consider the multiplication of two

n

-bit integer numbers

A

(multiplicand) and

B

(multiplier) in 2’s complement represen-tation, i.e.,

A

=

−

a

n

−

1

2

n

−

1

+

n

−

2

i

=0

a

i

2

i

B

=

−

b

n

−

1

2

n

−

1

+

n

−

2

i

=0

b

i

2

i

.

(1)In MBE,

B

in (1) becomes

B

=

n/

2

−

1

i

=0

m

i

2

2

i

=

n/

2

−

1

i

=0

(

−

2

b

2

i

+1

+

b

2

i

+

b

2

i

−

1

)2

2

i

(2)where

b

−

1

= 0

, and

m

i

∈ {−

2

,

−

1

,

0

,

1

,

2

}

. According to theencoded results from

B

, the Booth selectors choose

−

2

A

,

−

A

,0,

A

, or

2

A

to generate the partial product rows, as shown inTable I. The

2

A

in Table I is obtained by left shifting

A

onebit. Negation operation is achieved by complementing each bitof

A

(one’s complement) and adding “1” to the least signiﬁcantbit. Adding “1” is implemented as a correction bit

neg

, whichimplies that the partial product row is negative

(

neg

= 1)

orpositive

(

neg

= 0)

. In addition, because partial product rowsare represented in 2’s complement representation and every rowis left shifted two bit positions with respect to the previous row,sign extensions are required to align the most signiﬁcant partsof partial product rows. These extra sign bits will signiﬁcantlycomplicate the reduction tree. Therefore, many sign extensionschemes [3], [9]–[11] have been proposed to prevent extendingup the sign bit of each row to the

(2

n

−

1)

th bit position.Fig. 1(a) illustrates the MBE partial product array for an8

×

8 multiplier with a sign extension prevention procedure,where

s

i

is the sign bit of the partial product row PP

i

,

s

i

is thecomplement of

s

i

, and

b

_

p

indicates the bit position. As can beseen in Fig. 1(a), MBE reduces the number of partial productrows by half, but the correction bits result in an irregular partialproduct array and one additional partial product row. To have amore regular least signiﬁcant part of each partial product rowPP

i

, the authors in [7] added the least signiﬁcant bit

p

i

0

with

neg

i

in advance and obtained a new least signiﬁcant bit

τ

i

0

Fig. 2. Proposed MBE partial product array for 8

×

8 multiplication.

and a carry

c

i

. Note that both

τ

i

0

and

c

i

are generated no laterthan other partial product bits. Fig. 1(b) depicts the 8

×

8 MBEpartial product array generated by the approach proposed in [7].Since

c

i

is at the left one bit position of

neg

i

, the required addi-tions in the reduction tree are reduced. However, the approachdoes not remove the additional partial product row PP

4

.The problem is overcome in [8] by directly producing the2’s complement representation of the last partial product rowPP

n/

2

−

1

while the other partial products are produced so thatthe last

neg

bit will not be necessary. An efﬁcient method andcircuitaredevelopedin[8]toﬁndthe2’scomplementofthelastpartial product row in a logarithmic time. As shown in Fig. 1(c),the 10-bit last partial product row and its

neg

bit in Fig. 1(a)are replaced by the 10-bit 2’s complemented partial products

(

s

3

,s

3

,t

7

,t

6

,...,t

0

)

without the last

neg

bit. Note that oneextra “1” is added at the fourteenth bit position to obtain thecorrect ﬁnal product. The approach simpliﬁes and speeds upthe reduction step, particularly for a multiplier that is in the sizeof a power of 2 and uses 4–2 compressors [12], [13] to achievemodularity and high performance. However, the approach mustadditionally develop and design the 2’s complement logic,whichpossiblyenlargestheareaanddelayofthepartialproductgenerator and lessens the beneﬁt contributed by removing theextra row.III. P

ROPOSED

M

ULTIPLIERS

The proposed MBE multiplier combines the advantages of these two approaches presented in [7] and [8] to produce a veryregular partial product array, as shown in Fig. 2. In the partialproduct array, not only each

neg

i

is shifted left and replacedby

c

i

but also the last

neg

bit is removed by using a simpleapproach described in detail in the following section.

A. Proposed MBE Multiplier

For MB recoding, at least three signals are needed to repre-sent the digit set

{−

2

,

−

1

,

0

,

1

,

2

}

. Many different ways havebeen developed, and Table I shows the encoding scheme pro-posed in [14] that is adopted to implement the proposed MBEmultiplier. The Booth encoder and selector circuits proposed in[14] are depicted in Fig. 3(a) and (b), respectively. Based on therecoding scheme and the approach proposed in [7],

τ

i

0

and

c

i

inFig. 1(b) can be derived from the truth table shown in Table II,as follows:

τ

i

0

=

one

i

·

a

0

=

one

i

+

a

0

(3)

c

i

=

neg

i

·

(

one

i

+

a

0

) =

neg

i

+

one

i

·

a

0

.

(4)

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406 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 56, NO. 5, MAY 2009

Fig. 3. MBE encoder and selector proposed in [14].TABLE IIT

RUTH

T

ABLE FOR

P

ARTIAL

P

RODUCT

B

ITS IN THE

P

ROPOSED

P

ARTIAL

P

RODUCT

A

RRAY

According to (3) and (4),

τ

i

0

and

c

i

can be produced by one

NOR

gate and one

AOI

gate, respectively. Moreover, they aregenerated no later than other partial product bits.To further remove the additional partial product row PP

n/

2

[i.e., PP

4

in Fig. 1(b)], we combine the

c

i

for

i

=

n/

2

−

1

withthe partial product bit

p

i

1

to produce a new partial productbit

τ

i

1

and a new carry

d

i

. Then, the carry

d

i

can be incor-porated into the sign extension bits of PP

0

. However, if

τ

i

1

and

d

i

are produced by adding

c

i

and

p

i

1

, their arrival delays willprobably be larger than other partial product bits. Therefore,we directly produce

τ

i

1

and

d

i

for

i

=

n/

2

−

1

from

A

,

B

, andthe outputs of the Booth encoder (i.e.,

neg

i

,

two

i

, and

one

i

), asshowninTableII,where

and

denotetheExclusive-

OR

andExclusive-

NOR

operations, respectively. The logic expressionsof

τ

i

1

and

d

i

can be written as

τ

i

1

=

one

i

·

ε

+

two

i

·

a

0

= (

one

i

+

ε

)

·

(

two

i

+

a

0

)

(5)

d

i

=(

b

2

i

+1

+

a

0

)

·

[(

b

2

i

−

1

+

a

1

)

·

(

b

2

i

+

a

1

)

·

(

b

2

i

+

b

2

i

−

1

)]

(6)where

ε

=

a

1

,

if

a

0

·

b

2

i

+1

= 0

a

1

,

otherwise.(7)Since the weight of

d

i

is

2

n

, which is equal to the weightof

s

0

at bit position

n

,

d

i

can be incorporated with the signextension bits

s

0

s

0

s

0

of PP

0

. Let

α

2

α

1

α

0

be the new bitsafter incorporating

d

i

into

s

0

s

0

s

0

; the relations between themare summarized in Table III. As can be seen in Table III, themaximal value of

s

0

s

0

s

0

is 100 so that the addition of

s

0

s

0

s

0

and

d

i

will never produce an overﬂow. Therefore,

α

2

α

1

α

0

is

TABLE IIIT

RUTH

T

ABLE FOR

N

EW

S

IGN

E

XTENSION

B

ITS

Fig. 4. Proposed circuits to generate

τ

i

1

,

d

i

, and

α

2

α

1

α

0

for

i

=

n/

2

−

1

.

enough to represent the sum of

s

0

s

0

s

0

and

d

i

. According toTable III,

α

2

,

α

1

, and

α

0

can be expressed as

α

2

=(

s

0

·

d

i

)

(8)

α

1

=

s

0

·

d

i

=

α

2

(9)

α

0

=

s

0

d

i

.

(10)The corresponding circuits to generate

τ

i

1

,

d

i

, and

α

2

α

1

α

0

aredepicted in Fig. 4(a)–(c), respectively. The partial product arraygenerated by the proposed approach for the 8

×

8 multiplier isshown in Fig. 2. This regular array is generated by only slightlymodifying the original partial product generation circuits andintroducing almost no area and delay overhead.

B. Proposed Posttruncated MBE Multiplier

As mentioned earlier, the product of an

n

×

n

multiplier isfrequently rounded to

n

bits. A posttruncated multiplier can beaccomplished by adding a “1” at the

(

n

−

1)

th bit position of the partial product array and then truncating the least signif-icant

n

-bit of the ﬁnal

2

n

-bit product, as shown in Fig. 5(a).Unfortunately, this extra “1” will result in one additional partialproductrowlike

neg

n/

2

−

1

,anditcannotberemovedbydirectlyproducing the 2’s complement representation of the last partialproduct row PP

n/

2

−

1

.On the other hand, the proposed approach to remove

neg

n/

2

−

1

can easily be extended to simultaneously remove thisextra “1.” Because the weight of the extra “1” is equal to theweight of

p

i

1

for

i

=

n/

2

−

1

, we add the two least signiﬁcantbits

p

i

1

p

i

0

with the extra “1” and

neg

n/

2

−

1

beforehand toobtain a 2-bit sum

˜

τ

i

1

τ

i

0

and a carry

e

i

.

τ

i

0

can be generatedaccording to (3). Similar to

τ

i

1

and

d

i

,

˜

τ

i

1

and

e

i

for

i

=

n/

2

−

1

are directly produced from

A

,

B

, and the outputs of the Booth encoder to shorten their arrival delays. The relationsbetween them are also listed in Table II, and

˜

τ

i

1

and

e

i

can beobtained as follows:

˜

τ

i

1

=

τ

i

1

(11)

e

i

=(

κ

+

one

i

)

·

(

π

+

one

i

)

(12)

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