FPGA Implementation of Least Mean Square FIRAdaptive Filter Using Verilog HDL
Fahad -Al-Ghazali (F-05-CE-011), Muhammad Azam (F-05-CE-012)
Continuing Engineering, Semester FALL 05CASE, Islamabad
- FPGA (Field Programmable Gate Array)implementation of a simple 8-tap Least MeanSquare FIR adaptive filter is described.Architecture is mapped with Verilog and testedwith modelsim. Such type of filter has differentapplications in Image processing , speech/audio,Biomedical, instrumentation and control etc.
-FPGA, Verilog HDL, Modelsim, FIR ,LMS,etc.
An adaptive filter has an
that is meant to monitor theenvironment and vary the filter transferfunction accordingly.The basic operation now involves twoprocesses:1. a
process, which produces anoutput signal in response to a given inputsignal.2. an
process, which aims toadjust the filter parameters (filtertransfer function) to the (possibly time-varying) environment. The adaptation issteered by an error signal that indicateshow well the filter output matches somedesired response. A brief diagram of adaptive filter is given in Pic 1.
One of the successful adaptive algorithmis the LMS algorithm. It is a practicalmethod of obtaining estimates of filterweights
in real time in an easy way.The Widrow-Hopf LMS algorithm forupdating the weights from sample tosample is given by
The flow chart of this filter is shown inPic 2.