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Lec01 Intro

Lec01 Intro

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Published by: minhhai2209 on Aug 27, 2010
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CS162Operating Systems andSystems ProgrammingLecture 1What is an Operating System?
August 27
th
, 2008Prof. John Kubiatowiczhttp://inst.eecs.berkeley.edu/~cs162
Lec1.28/27/08Kubiatowicz CS162 ©UCB Fall 2008
Who am I?
Professor John Kubiatowicz (Prof “Kubi”)
Background in Hardware Design
»
Alewife project at MIT 
»
Designed CMMU, Modified SPAR C processor
»
Helped to write operating system
Background in Operating Systems
»
Worked for Project Athena (MIT)
»
OS Developer (device drivers,network file systems)
»
Worked on Clustered High-Availability systems(CLAM Associates)
»
OS lead researcher for the new Berkeley PARLab(Tessellation OS). More later.
Peer-to-Peer
»
OceanStoreproject Store your data for 1000 years
»
Tapestry and Bamboo –Find you data around globe
Quantum Computing
»
Well, this is just cool, but probably not apropos
 
 T  e s  s  e l     l     a t   i    o n  A l     e w i    f   e O c  e a n  S  t   o r  e
Lec1.38/27/08Kubiatowicz CS162 ©UCB Fall 2008
Goals for Today
What is an Operating System?
And what is it not?
Examples of Operating Systems design
Why study Operating Systems?
Oh, and “How does this class operate?”Interactive is important!Ask Questions!
Note: Some slides and/or pictures in the following areadapted from slides ©2005 Silberschatz, Galvin, and Gagne. Slidescourtesy of Kubiatowicz, AJ Shankar, George Necula, Alex Aiken,Eric Brewer, RasBodik, Ion Stoica, Doug Tygar, and David Wagner.
Lec1.48/27/08Kubiatowicz CS162 ©UCB Fall 2008
Technology Trends: Moore’s Law
2X transistors/Chip Every 1.5 years
Called “Moore’s Law
Moore’s Law
Microprocessors havebecome smaller, denser,and more powerful.
Gordon Moore (co-founder ofIntel) predicted in 1965 that thetransistor density ofsemiconductor chips woulddouble roughly every 18months.
 
Lec1.58/27/08Kubiatowicz CS162 ©UCB Fall 2008
Societal Scale Information Systems
Scalable, Reliable,Secure ServicesMEMS forSensor NetsInternetConnectivity
ClustersMassive Cluster 
Gigabit Ethernet
DatabasesInformation CollectionRemote StorageOnline GamesCommerce
The world is a large parallel system
Microprocessors in everything
Vast infrastructure behind them
 
Lec1.68/27/08Kubiatowicz CS162 ©UCB Fall 2008
People-to-Computer Ratio Over Time
Today: Multiple CPUs/person!
Approaching 100s?
From David Culler
Lec1.78/27/08Kubiatowicz CS162 ©UCB Fall 2008
1101001000100001978 1980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 2004 2006
   P  e  r   f  o  r  m  a  n  c  e   (  v  s .   V   A   X  -   1   1   /   7   8   0   )
25%/year52%/year??%/year
New Challenge: Slowdown in Joy’s law of Performance
VAX: 25%/year 1978 to 1986
RISC + x86: 52%/year 1986 to 2002
RISC + x86: ??%/year 2002 to present
From Hennessy and Patterson,
Computer Architecture: AQuantitative Approach
, 4th edition, Sept. 15, 2006
Sea change in chipdesign: multiple “cores”orprocessors per chip
3X
Lec1.88/27/08Kubiatowicz CS162 ©UCB Fall 2008
ManyCoreChips: The future is here
“ManyCore”refers to many processors/chip
64? 128? Hard to say exact boundary
How to program these?
Use 2 CPUs for video/audio
Use 1 for word processor, 1 for browser
76 for virus checking???
Parallelism must be exploited at all levels
Intel 80-core multicorechip (Feb 2007)
80 simple cores
Two floating point engines /core
Mesh-like "network-on-a-chip“
100 million transistors
65nm feature size
Frequency Voltage Power Bandwidth Performance3.16 GHz 0.95 V 62W 1.62 Terabits/s 1.01 Teraflops5.1 GHz 1.2 V 175W 2.61 Terabits/s 1.63 Teraflops5.7 GHz 1.35 V 265W 2.92 Terabits/s 1.81 Teraflops
 
Lec1.98/27/08Kubiatowicz CS162 ©UCB Fall 2008
Another Challenge: Power Density
Moore’s Law Extrapolation
Potential power density reaching amazing levels!
Flip side: Battery life very important
Moore’s law can yield more functionality at equivalent(or less) total energy consumption
Lec1.108/27/08Kubiatowicz CS162 ©UCB Fall 2008
Computer System Organization
Computer-system operation
One or more CPUs, device controllers connectthrough common bus providing access to sharedmemory
Concurrent execution of CPUs and devicescompeting for memory cycles
Lec1.118/27/08Kubiatowicz CS162 ©UCB Fall 2008
Functionality comes with great complexity!
ProcCachesBussesMemoryI/O Devices:ControllersadaptersDisksDisplaysKeyboardsNetworks
Pentium IV Chipset
Lec1.128/27/08Kubiatowicz CS162 ©UCB Fall 2008
Sample of Computer Architecture Topics
Instruction Set Architecture
Pipelining, Hazard Resolution,Superscalar, Reordering,Prediction, Speculation,Vector, Dynamic CompilationAddressing,Protection,Exception HandlingL1 CacheL2 CacheDRAMDisks, WORM, TapeCoherence,Bandwidth,LatencyEmerging TechnologiesInterleavingBus protocolsRAIDVLSIInput/Output and StorageMemoryHierarchyPipelining and InstructionLevel ParallelismNetworkCommunication
  O  t  h  e  r  P  r  o  c  e  s  s  o  r  s

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