Welcome to Scribd, the world's digital library. Read, publish, and share books and documents. See more
Download
Standard view
Full view
of .
Look up keyword
Like this
1Activity
0 of .
Results for:
No results containing your search query
P. 1
lec14-demandpage

lec14-demandpage

Ratings: (0)|Views: 7|Likes:
Published by minhhai2209

More info:

Published by: minhhai2209 on Aug 27, 2010
Copyright:Attribution Non-commercial

Availability:

Read on Scribd mobile: iPhone, iPad and Android.
download as PDF, TXT or read online from Scribd
See more
See less

08/27/2010

pdf

text

original

 
CS162Operating Systems andSystems ProgrammingLecture 14Caching andDemand Paging
October 20, 2008Prof. John Kubiatowiczhttp://inst.eecs.berkeley.edu/~cs162
Lec14.210/20/08Kubiatowicz CS162 ©UCB Fall 2008
Review: Memory Hierarchy of a Modern Computer System
Take advantage of the principle of locality to:
Present as much memory as in the cheapest technology
Provide access at speed offered by the fastest technology
 On- Ci     p C a c  e R e   gi    s  t    e  s 
ControlDatapathSecondaryStorage(Disk)ProcessorMainMemory(DRAM)SecondLevelCache(SRAM)
1s10,000,000s(10s ms)Speed (ns):10s-100s100s100sGsSize (bytes):Ks-MsMs
TertiaryStorage(Tape)
10,000,000,000s(10s sec)TsLec14.310/20/08Kubiatowicz CS162 ©UCB Fall 2008
Compulsory(cold start): first reference to a block
“Coldfact of life: not a whole lot you can do about it
Note: When running “billions”of instruction, CompulsoryMisses are insignificant
Capacity:
Cache cannot contain all blocks access by the program
Solution: increase cache size
Conflict(collision):
Multiple memory locations mapped to same cache location
Solutions: increase cache size, or increase associativity
Two others:
Coherence(Invalidation): other process (e.g., I/O)updates memory
Policy: Due to non-optimal replacement policy
Review: A Summary on Sources of Cache Misses
Lec14.410/20/08Kubiatowicz CS162 ©UCB Fall 2008
Goals for Today
Finish discussion of Caching/TLBs
Concept of Paging to Disk
Page Faults and TLB Faults
Precise Interrupts
Page Replacement Policies
Note: Some slides and/or pictures in the following areadapted from slides ©2005 Silberschatz, Galvin, and GagneNote: Some slides and/or pictures in the following areadapted from slides ©2005 Silberschatz, Galvin, and Gagne.Many slides generated from my lecture notes by Kubiatowicz.
 
Lec14.510/20/08Kubiatowicz CS162 ©UCB Fall 2008
Cache Index0431Cache TagByte Select8Cache DataCache Block 0Cache TagValid
:: :
Cache DataCache Block 0Cache Tag Valid
: ::
Mux
01Sel1 Sel0
OR
 
Hit
Review: Set Associative Cache
N-way set associative: N entries per Cache Index
N direct mapped caches operates in parallel
Example: Two-way set associative cache
Cache Index selects a “set”from the cache
Two tags in the set are compared to input in parallel
Data is selected based on the tag result
CompareCompareCache Block
Lec14.610/20/08Kubiatowicz CS162 ©UCB Fall 2008
Example: Block 12 placed in 8 block cache
0 1 2 3 4 5 6 7Blockno.
Direct mapped:
block 12 can goonly into block 4(12 mod 8)
Set associative:
block 12 can goanywhere in set 0(12 mod 4)
0 1 2 3 4 5 6 7Blockno.Set0Set1Set2Set3
Fully associative:
block 12 can goanywhere
0 1 2 3 4 5 6 7Blockno.0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
32-Block Address Space:
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3Blockno.
Review: Where does a Block Get Placed in a Cache?
Lec14.710/20/08Kubiatowicz CS162 ©UCB Fall 2008
Easy for Direct Mapped: Only one possibility
Set Associative or Fully Associative:
Random
LRU (Least Recently Used)
2-way 4-way 8-waySizeLRURandomLRURandomLRURandom
16 KB5.2%5.7%4.7%5.3%4.4%5.0%64 KB1.9%2.0%1.5%1.7%1.4%1.5%256 KB1.15%1.17%1.13%1.13%1.12%1.12%
Which block should be replaced on a miss?
Lec14.810/20/08Kubiatowicz CS162 ©UCB Fall 2008
Write through: The information is written to both theblock in the cache and to the block in the lower-levelmemory
Write back: The information is written only to theblock in the cache.
Modified cache block is written to main memory onlywhen it is replaced
Question is block clean or dirty?
Pros and Cons of each?
WT:
»
PRO: read misses cannot result in writes
»
CON: Processor held up on writes unless writes buffered
WB:
»
PRO: repeated writes not sent to DRAMprocessor not held up on writes
»
CON: More complexRead miss may require writebackof dirty data
What happens on a write?

You're Reading a Free Preview

Download
scribd
/*********** DO NOT ALTER ANYTHING BELOW THIS LINE ! ************/ var s_code=s.t();if(s_code)document.write(s_code)//-->