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Simple VHDL Examples

Simple VHDL Examples

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Published by Amit Pathak

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Published by: Amit Pathak on Sep 02, 2010
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10/30/2011

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For further assistance, email
support_center@synopsys.com
or call your local support center
 HOME CONTENTS INDEX
A
Examples
Source files for examples demonstrating the use of VHDL are inthe
/synopsys/syn/examples/vhdl
directory. The examples are
 
Moore Machine
 
Mealy Machine
 
Read–Only Memory (ROM)
 
Waveform Generator
 
Smart Waveform Generator
 
Definable-Width Adder-Subtracter
 
Count Zeros — Combinational Version
 
Count Zeros — Sequential Version
 
Soft Drink Machine — State Machine Version
 
Soft Drink Machine — Count Nickels Version
 
Carry-Lookahead Adder
 
Serial-to-Parallel Converter — Counting Bits
 
Serial-to-Parallel Converter — Shifting Bits
 
Programmable Logic Array (PLA)
 
VHDL Compiler ReferenceV3.4
For further assistance, email
support_center@synopsys.com
or call your local support center
 HOME CONTENTS INDEX
Moore Machine
Figure A1 is a diagram of a simple Moore finite-state ma-chine. It has one input (
X
), four internal states (
S0
to
S3
), andone output (
Z
).
Figure A1Moore Machine Specification 
S0S1S3S2011001101010PresentNextOutputstatestate (Z)X=0X=1X=0S0S0S20S1S0S21S2S2S31S3S3S10
The VHDL code implementing this finite-state machine isshown in Example A1, which includes a schematic of thesynthesized circuit.The machine is described with two processes. One processdefines the synchronous elements of the design (state regis-ters); the other process defines the combinational part of thedesign (state assignment
case
statement). See the discussionunder wait Statement” in Chapter 6 for more details onusing the two processes.
 
VHDL Compiler ReferenceV3.4
For further assistance, email
support_center@synopsys.com
or call your local support center
 HOME CONTENTS INDEX
Example A–1Implementation of a Moore Machine 
entity MOORE is –– Moore machineport(X, CLOCK: in BIT;Z: out BIT);end;architecture BEHAVIOR of MOORE istype STATE_TYPE is (S0, S1, S2, S3);signal CURRENT_STATE, NEXT_STATE: STATE_TYPE;begin–– Process to hold combinational logicCOMBIN: process(CURRENT_STATE, X)begincase CURRENT_STATE iswhen S0 =>Z <= ’0’;if X = ’0’ thenNEXT_STATE <= S0;elseNEXT_STATE <= S2;end if;when S1 =>Z <= ’1’;if X = ’0’ thenNEXT_STATE <= S0;elseNEXT_STATE <= S2;end if;when S2 =>Z <= ’1’;if X = ’0’ thenNEXT_STATE <= S2;elseNEXT_STATE <= S3;end if;when S3 =>Z <= ’0’;if X = ’0’ thenNEXT_STATE <= S3;elseNEXT_STATE <= S1;end if;end case;end process;

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