Introducing the Peripheral Component Interconnect (PCI) Bus

PCI Definition

PCI stands for Peripheral Component Interconnect. The PCI Local Bus Standard was
introduced by Intel Corporation in 1993. PCI is an I/O bus. I/O busses are used to
connect various types of Input/Output devices in a computer system. I/O busses can
have many different types of devices connected to them and can provide different
bandwidth to the different devices. Since 1993 use of the PCI Local Bus Standard has
become very widespread. Nearly all modern PCs and Macintosh computers utilize the
PCI local bus standard. PCI is an aging standard and it's replacement, PCI Express, is
scheduled for release in 2003. Despite this fact, the huge base of devices currently
designed to use the PCI Local Bus Standard ensures that PCI will be implemented in
most personal computer systems for years to come

PCI Purpose

The purpose of the PCI local bus standard is to provide a means of transferring data
between devices in a computer.

PCI Bus Demystified:

Typically, the processor is connected at one end of these wires. Memory may also be
attached via the bus.
The wires are split into several functional groups such as:
_ Address: Specifies the peripheral and register within the peripheral that is

being accessed.
_ Data: The information being transferred to or from the peripheral

_ Control: Signals that effect the data transfer operation. It is the control signals

and how they are manipulated that embody the bus protocol.
Beyond basic data transfer, busses typically incorporate advanced features such as:
_ Interrupts

_ DMA

_ Power distribution

Additional control lines manage these features.

The classic concept of a bus is a set of boards plugged into a passive backplane as
shown in Figure 1-1. But there are also many bus implementations based on cables
interconnecting stand-alone boxes.

• What makes the PCI bus one of the fastest I/O bus used today?
• Three features make this possible:
– Burst Mode: allows multiple sets of data to be sent (Kozierok, 2001a)
– Full Bus Mastering: the ability of devices on the PCI bus to perform transfers
directly (Kozierok, 2001c)
– High Bandwidth Options: allows for increased speed of the PCI (Kozierok,
2001a)
Plug and Play
• Requirements for full implementation:
– Plug and Play BIOS
– Extended System Configuration Data (ESCD)
– Plug and Play operating system
• Tasks it automates:
– Interrupt Requests (IRQ)
– Direct Memory Access (DMA)
– Memory Addresses
– Input/Output (I/O) Configuration

How PCI Works: Installing A New Device

Once a new device has been inserted into a PCI slot on the motherboard
1. Operating System Basic Input/Output System (BIOS) initiates Plug and Play (PnP) BIOS.
2. PnP BIOS scans the PCI bus for any new hardware connected to the bus. If new hardware is
found, it will ask for identification.
3.The device will respond with its identification and send its device ID to the BIOS through the
bus.
4.PnP checks the Extended System Configuration Data (ESCD) to make sure the configuration
data already exists for the card. (If the card is new, then there will be no data for it.)
5. PnP will assign an Interrupt Request Line, Direct Memory Access, memory address and
Input/Output settings to the card, then stores the information in the ESCD.
6. When the Windows software loads, it will check the PCI bus and the ESCD to see if there is
new hardware. Windows will alert the user that new hardware has been found if there is new
hardware installed and will also identify the hardware.

How a Device Works:

• Example: PCI-based sound card
1. The sound card will convert the analog signal to a digital signal.
2. The digital audio data carried across the PCI bus to the bus controller, which
determines which device on the PCI device has the priority to send data to the central
processing unit (CPU) and whether the data will go directly to the CPU or to the
system memory.
3. If the sound card is in recording mode, the bus controller will assign a high priority to
the data coming from the sound card. It will send the sound cards data over the bus
bridge to the system bus.
4. The system bus will save the data in system memory. When the recording is
complete, then it will be up to the user to save the data from the sound card on either
the hard drive, or will remain in memory for additional processing.

Interrupts
Devices are required to follow a protocol so that the interrupt lines can be shared.
The PCI bus includes four interrupt lines, all of which are available to each device.
However, they are not wired in parallel as are the other PCI bus lines. The positions of the
interrupt lines rotate between slots, so what appears to one device as the INTA# line is
INTB# to the next and INTC# to the one after that. Single-function devices use their
INTA# for interrupt signaling, so the device load is spread fairly evenly across the four
available interrupt lines. This alleviates a common problem with sharing interrupts.

PCI bridges (between two PCI buses) map the four interrupt traces on each of their
sides in varying ways. Some bridges use a fixed mapping, and in others it is configurable.
In the general case, software cannot determine which interrupt line a device's INTA# pin is
connected to across a bridge. The mapping of PCI interrupt lines onto system interrupt
lines, through the PCI host bridge, is similarly implementation-dependent. The result is that
it can be impossible to determine how a PCI device's interrupts will appear to software.
Platform-specific BIOS code is meant to know this, and set a field in each device's
configuration space indicating which IRQ it is connected to, but this process is not reliable.

PCI interrupt lines are level-triggered. This was chosen over edge-triggering in
order to gain an advantage when servicing a shared interrupt line, and for robustness: edge
triggered interrupts are easy to miss.

PCI Express does not have physical interrupt lines at all. It uses message-signaled
interrupts exclusively.