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VHDL Tutorial

VHDL Tutorial

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VHDL
Tutorial: Learn byExample
 
--
by Weijun Zhang
 
If we hear, we forget; if we see, we remember; if we do, we understand.
 
--
Proverb
Table of Contents
ForewordBasic Logic Gates
 
Combinational LogicDesign
 
Typical CombinatinalLogic ComponentsLatch and Flip-Flops
 
Sequential Logic DesignTypical SequentialLogic ComponentsCustom Single-Purpose Processor Design
 
General-Purpose Processor Design
 
Appendix: Modeling an industry core
Foreword (by Frank Vahid)
<> HDL (Hardware Description Language) based design hasestablished itself as the modern approach to design of digitalsystems, with VHDL (VHSIC Hardware Description Language) andVerilog HDL being the two dominant HDLs. Numerous universitiesthus introduce their students to VHDL (or Verilog). The problem isthat VHDL is complex due to its generality. Introducing students tothe language first, and then showing them how to design digitalsystems with the language, tends to confuse students. The languageissues tend to distract them from the understanding of digitalcomponents. And the synthesis subset issues of the language add tothe confusion.We developed the following tutorial based on the philosophy that the
 
beginning student need not understand the details of VHDL --instead, they should be able to modify examples to build the desiredbasic circuits. Thus, they learn the importance of HDL-based digitaldesign, without having to learn the complexities of HDLs. Thosecomplexities can be reserved for a second, more advanced course. The examples are mostly from the textbook
by Frank Vahid and Tony Givargis. They start from basicgates and work their way up to a simple microprocessor. Most of theexamples have been simulated byAldecActiveHDL Simulator andSynopsysDesign Analyzer, as well as synthesized with SynopsysDesign Compiler . Several sequential design examples have beensuccessfully tested onXilinxFoundation Software and FPGA/CPLDboard.
Basic Logic Gates
 
(ESD Chapter 2: Figure 2.3)
Every VHDL design description consists of at least one
entity / architecture
pair, orone entity with multiple architectures. The entity section of the HDL design is usedto declare the
I/O ports
of the circuit, while the description code resides withinarchitecture portion. Standardized design libraries are typically used and areincluded prior to the entity declaration. This is accomplished by including the code"library ieee;" and "use ieee.std_logic_1164.all;".
 
Driver
BehaviorCodeBehaviorSimulation 
Inverter
BehaviorCodeBehaviorSimulation
OR gate
BehaviorCodeBehaviorSimulation 
NOR gate
BehaviorCodeBehaviorSimulation
ANDgate
BehaviorCodeBehaviorSimulation
NANDgate
BehaviorCodeBehaviorSimulation
XOR gate
BehaviorCodeBehaviorSimulation 
XNOR gate
BehaviorCodeBehaviorSimulation
Combinational Logic Design
 
(ESD Chapter 2: Figure 2.4)
We use
 port map statement 
to achieve the
structural model
(componentsinstantiations). The following example shows how to write the program toincorporate multiple components in the design of a more complex circuit. In orderto simulate the design, a simple
test bench
code must be written to apply asequence of inputs (Stimulators) to the circuit being tested (
UUT 
). The output of the test bench and UUT interaction can be observed in the simulation waveformwindow.
CombinationalLogic
BehaviorCodeTestBenchBehaviorSimulationSynthesisSchematicGate-levelSimulation
Tri-State Driver
BehaviorCodeTestBenchBehaviorSimulationSynthesisSchematicGate-levelSimulation
Discussion I: Signal vs. Variable
:
 
Siganls
are used to connect the design components and must carry theinformation between current statements of the design. On the other hand,
variables
are used within process to compute certain values. The followingexample shows their difference:
Signal/VariableExample
BehaviorCodeBehaviorSimulation
Typical Combinational Components
 
(ESD Chapter 2: Figure 2.5)
 The following behavior style codes demonstrate the concurrent and sequentialcapabilities of VHDL. The
concurrent statements
are written within the body of anarchitecture. They include
concurrent signal assignment 
,
concurrent process
and
component instantiations (port map statement)
.
Sequential statements
are writtenwithin a
 process
statement,
function
or
 procedure
. Sequential statement include
case statement 
,
if-then-else statement 
and
loop statement 
.
 
Multiplexor
BehaviorCodeTestBenchBehaviorSimulationSynthesisSchematicGate-levelSimulation
Decoder
BehaviorCodeTestBenchBehaviorSimulationSynthesisSchematicGate-levelSimulation
Adder
BehaviorCodeTestBenchBehaviorSimulationSynthesisSchematicGate-levelSimulation
Comparator
BehaviorCodeTestBenchBehaviorSimulationSynthesisSchematicGate-levelSimulation
ALU
BehaviorCodeTestBenchBehaviorSimulationSynthesisSchematicGate-levelSimulation
Multiplier
BehaviorCodeTestBenchBehaviorSimulationSynthesisSchematicGate-levelSimulation
Latch & Flip-Flops
 
(ESD Chapter 2.3)
Besides from the circuit input and output signals, there are normally two otherimportant signals,
reset 
and
clock 
, in the sequential circuit. The reset signal iseither
active-high
or
active-low
status and the circuit status transition can occur ateither clock
rising-edge
or
falling-edge
. Flip-Flop is a basic component of thesequential circuits.
 
SimpleLatch
BehaviorCodeTestBenchBehvaiorSimulationGate-levelImplementationGate-levelSimulation
D Flip-Flop
BehaviorCodeTestBenchBehaviorSimulationGate-levelImplementationGate-levelSimulation
JK Flip-Flop
BehaviorCodeTestBenchBehaviorSimulationGate-levelImplementationGate-levelSimulation
Typical Sequential Components
 
(ESD Chapter 2: Figure 2.6)
 Typical sequential components consist of registers, shifters and counters. Theconcept of 
generics
is often used to parameterize these components.

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