Welcome to Scribd, the world's digital library. Read, publish, and share books and documents. See more
Download
Standard view
Full view
of .
Look up keyword
Like this
2Activity
0 of .
Results for:
No results containing your search query
P. 1
Design of a FPGA Controller for Full Bridge Phase

Design of a FPGA Controller for Full Bridge Phase

Ratings: (0)|Views: 32|Likes:
Published by vuhoanganh110
Design of a FPGA controller for full bridge is very good
Design of a FPGA controller for full bridge is very good

More info:

Published by: vuhoanganh110 on Sep 13, 2010
Copyright:Attribution Non-commercial

Availability:

Read on Scribd mobile: iPhone, iPad and Android.
download as PDF, TXT or read online from Scribd
See more
See less

09/20/2010

pdf

text

original

 
Design of a FPGA Controller for Full Bridge Phase-Shifted Zero VoltageSwitching DC/DC Power Converters
Hao Li and Qin JiangSchool of Communications and InformaticsVictoria University, P.O. Box 14428,Melbourne City MC 8001, Vic. AustraliaEmail: jq@cabsav.vu.edu.au
Abstract
The paper describes the development of a FPGA (Field Programmable Gate Array) digitalcontroller for the control of a full bridge phase-shifted zero voltage switching (FPZVS) dc/dcpower converter. The merits of the FPGA technology are its flexibility, intelligence and amuch faster speed than that of a DSP type digital controller. The design details are presentedin this paper based on a 500 W, 500 kHz model converter. The simulation results of both thecontroller and the converter are presented using the Xilinx Foundation Series environment andthe PSpice software respectively.
1. INTRODUCTION
The switching mode power supply (SMPS)operating at a high frequency can provide smallsize and weight, as the filtering inductance andcapacitance are reduced and power density isincreased. However, a high switching frequencyresults in high switching losses which reduce theefficiency of the converter. To overcome thisdilemma the soft-switching techniques wereintroduced [1-5], such as the Zero VoltageSwitching (ZVS) techniques which can be used toincrease the converter efficiency at high switchingfrequencies [3-5]. In this technique, effects of theparasitic circuit elements are used advantageouslyto facilitate the resonant transitions as opposed tobeing dissipatively snubbed. The resonant tank functions to position zero voltage across theswitching device prior to turn-on, eliminating anypower loss due to the simultaneous overlap of switch current and voltage at each transition [4].Not only the switching losses but also the RadioFrequency Interference (RFI) and the Electro-Magnetic Interference (EMI) are significantlyreduced. The requirement of power MOSFETswitches dissipation is reduced as well and theconversion efficiency is increased significantly.Most of FPZVS converters on the market use theanalog controller of integrated circuit fromcompanies like Unitrode, Motorala and etc [1-5].Typically two ICs are used, for instance, UC3875IC generates the gate drive signal to the MOSFETs,and the TL074 IC implements the control loopregulators [4]. Analog controllers can provide thefastest control loop update compared with digitalcontrollers. However, as they are designed andimplemented with hardware only, it takes a longdesign cycle and lacks flexibility and intelligence.The application of digital controllers using digitalsignal processor to the control of FPZVS converterswas reported [6]. Where the control law is softwareprogrammed, this allows for advanced controlalgorithm such as predictive and adaptive controlsto be implemented. Also the non-linear dependenceof the desired duty factor on the input and outputvoltages of the converter can be easily taken intoaccount in the software programming. This is notpossible with the analog controllers. However,given the switching frequencies 500 kHz plus forthe ZVS technology, the speed of DSP may be notsufficiently high to implement advanced controlalgorithms.In this paper, the application of the latest PLD(Programmable Logic Device) technology into thecontrol of the FPZVS power converter is explored.The technology features combined merits of bothanalog and DSP controllers, in that its designprocess is that of computer programming using C-like high level language. Whereas its speed ismuch faster than DSP. The throughput time of thePLD controller is found approximate to theconversion time of Analog/Digital converters inuse.In what follows, the operation principle of theFPZVS converter is described first, features to betaken into account in the design process of thedigital controller are highlighted. The designexample of the FPGA digital controller based on amodel converter is then discussed. Finally thesimulation results are presented.
 
2. OPERATION PRINCIPLE OF THE FPZVSCONVERTER
Fig.1 gives the main circuit of the full bridge with azero voltage transition design. S
1
, S
2
, S
3
and S
4
arecontrolled switching devices, MOSFETs. D
1
, D
2
,D
3
and D
4
are body diodes of the MOSFETs. C
1
,C
2
, C
3
and C
4
are the equivalent parasitic outputcapacitance of the MOSFETs. T is the isolationtransformer. The inductance L equals L
c
+ L
t
,where L
c
is the commutation inductance and L
t
isthe leakage inductance of the transformer.Zero voltage transition requires each MOSFET tobe turned on and off when the voltage across itsdrain and source terminals, V
DS
, is zero.
Turn-off 
with a zero voltage is achieved by the existence of C
i
(i = 1, 2, 3, 4) as shown in Fig.1. When theMOSFET S
i
is conducting, C
i
is short-circuited, i.e.V
DSi
is zero. As the voltage across the C
i
cannotchange instantaneously, the MOSFET is alwaysturned off with a zero voltage.
Turn-on
with a zerovoltage however, requires a resonant process,during which C
i
of the incoming MOSFET’s S
i
discharges until its anti-parallel diode conductsprior to turn on, V
DSi
of the incoming switch is thenclamped to the diode’s conducting voltage [7].Power is only transferred to the output sectionduring the ON time of the diagonal switches, S
1
 /S
2
or S
3
 /S
4
of Fig.1. This is similar to a conventionalfull bridge converter, which alternately places thetransformer primary across the input supply V
i
forsome period of time. This duration is termed activestate.During the freewheeling period, either the top twoor the bottom two MOSFETs (S
2
 /S
3
or S
1
 /S
4
) areon, termed as the passive state. The load andmagnetizing currents can therefore continue to flowin the primary winding. In fact, their commutationto the secondary side is resisted by the leakageinductance, and the total resistance of thetransformer, the MOSFETs, and the diode rectifieris not large enough to force a significantcommutation during the freewheeling period [5].In Fig.1, the two legs of the bridge, leg A and leg Boperate under significantly different conditions.Depending on the switching sequence of S
1
throughS
4
, switching one of the legs moves the converterfrom the active state to the passive state. Whileswitching the other leg moves the converter fromthe passive state to the active state. The former istermed A–P leg and the latter the P–A leg.
TS1S3S4S2C1C3C4C2D1D3D4D2LD5D6Cf Lf RoVi+-+-IpVoAB
Fig.1 Topology of the full bridge phase shifted ZVSconverter.Minimum turn-on delay timeIn principle, to ensure loss-less transitions, theMOSFET must be turned on only when currentflows in its body diode, i.e. after its parasitic outputcapacitance is completely discharged and the outputcapacitance of the other MOSFET of the same legis charged up. The time it takes to complete theabove process is referred to as the minimum turn-on delay time, T
on-min
, which if associated with theP-A leg transition is greater than that of the A-P legtransition. Also it is proportional to V
i
and inverselyproportional to the load current. To minimize theconduction loss, the designed turn-on delay timeshould be based on the T
on-min
corresponding to thespecified load condition.The effective duty cycleThe FPZVS converter works at a fixed switchingfrequency, its operating duty cycle, D, isproportional to the on-pulse overlap between twodiagonal MOSFETs. Normally, one gating signal isfixed as a reference one, while the other is phaseshifted so that the duration of the on-pulse overlapof the two devices is varied. At the maximumoutput, the overlap is maximum and vice versa.In Fig.2, the gating signals (top four traces) S
1
through S
4
over one power transfer cycle areillustrated, where the turn-on time delays betweentwo pair of diagonal switches S
1
 /S
2
and S
3
 /S
4
are(t
13
– t
10
) and (t
5
t
2
) respectively, correspondingto the amount of the phase shift implemented.
 
t70t2t3t6t5t0S4S1S3S2t1t4slope = Vi / ( Lc + Lt )slope = ( Vi - Vo ) / ( Lc + Lt + Lf )slope = Vo / Lf IpVA-B0Vst8Ts/2
 
DoTs/2DTs/2DeTs/2Vit-Vi-Ipa-Iaptt10t13
Fig.2 Gate timing and typical waveforms.Responses associated with the voltage and currentat the primary terminals of the transformer, V
A-B
and I
p
, are given as two middle traces of Fig.2respectively. Please note that the finite slope of therising and falling edges of the primary current, I
P,
results in the loss of the duty cycle D
o
. Theeffective duty cycle D
e
is therefore reflected fromthe pulse width of the secondary voltage, V
s,
shownas the bottom trace of Fig.2. The differencebetween D and D
e
is thus
oe
D D D
+=
(1)The effective voltage gain of the converter can beexpressed based on the effective duty cycle D
e.
e psio
 D N  N 
=
(2)where N
p
and N
s
are turns of the primary and thesecondary windings of the transformer respectively.The expression of D can be derived from Fig.1 andFig.2 as follows
o f ciosco  f co
 L L L N  I  f  L L  L L L N  D
+++ +=
)()(4)(
2
(3)where
ss
 f 
1
=
– the switching frequency and
s p
 N  N  N 
=
– the transformer turns ratio.The last equation indicates that the duty cycle Ddepends non-linearly on the input and outputvoltages of the converter. To realize this controllaw with an analog controller would becomplicated. While the digital control offers thepossibility to program the equation in software.The minimum turn on delay and the effective dutycycle can be easily taken into account in the designof a digital controller.
3. DESIGN OF THE DIGITAL CONTROLLER
500 W Model ConverterA 500 W, 400/40 V FPZVS power converter hasbeen designed in this study, however, design detailsare beyond the scope of this paper, parameters of the converter are listed bellow instead:MOSFET device IRF840;switching frequency = 500 kHz;commutating inductor L
c
= 14
µ
H;output filtering inductor L
= 6.2
µ
H;output filtering capacitor C
= 6.5
µ
F;load resistance R
o
= 3
;fixed individual switching duty cycle = 48%;maximum phase shift duty cycle = 88%;minimum turn on delay = 40 ns
3.1 The software programming
The block diagram of the FPGA controlled FPZVSconverter is given in Fig.3. The design of thecontroller is a process of computer programmingusing the C-like VHDL code. There are 3concurrent processes embedded in the program, thecontrol cycle, the reference gating signal generationand the phase shift implementation respectively.They are to be detailed in what follows.Control CycleThe command phase shift duty cycle at i
th
samplingcycle, D
i
, is calculated based on the feedback signals V
o
and I
as shown in Fig.3. The currentcontrol mode is implemented with a band-bandcontrol algorithm as follows:If (I
m
– I
) > 0, D
i
= D
i-1
+ k 
1
×
sign (V
ref 
– V
o
)Otherwise D
i
= D
i-1
+ k 
2
 
×
sign (I
m
– I
)Where k 
1
and k 
2
are control constant representingthe step change in D
i-1
, V
o
is the output voltage, V
ref 
is the reference of V
o
, I
is the filter inductor currentand I
m
is the upper limit of I
.

You're Reading a Free Preview

Download
scribd
/*********** DO NOT ALTER ANYTHING BELOW THIS LINE ! ************/ var s_code=s.t();if(s_code)document.write(s_code)//-->