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Table Of Contents

1.0DEVICE OVERVIEW
1.1Enhanced Mid-range CPU
2.0MEMORY ORGANIZATION
2.5Indirect Addressing, INDF and FSR Registers
3.0RESETS
3.3Power-up Timer (PWRT)
3.4Watchdog Timer (WDT)
3.5Brown-Out Reset (BOR)
3.6Reset Instruction
3.7Stack Overflow/Underflow
3.8Power-Up Time-out Sequence
4.0INTERRUPTS
4.5.1 INTCON REGISTER
5.0LOW DROPOUT (LDO) VOLTAGE REGULATOR
6.0I/O PORTS
6.1Alternate Pin Function
6.2PORTA Registers
6.2.1 ANSELA REGISTER
6.3.2 INTERRUPT-ON-CHANGE
6.3.3 ANSELB REGISTER
6.5.1 ANSELD REGISTER
6.6.1 ANSELE REGISTER
7.0INTERRUPT-ON-CHANGE
8.0OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR)
8.4.4 EXTERNAL RC MODE
8.5Internal Clock Modes
8.5.5 OSCSTAT REGISTER
8.5.6 OSCTUNE REGISTER
8.5.8 INTERNAL OSCILLATOR CLOCK SWITCH TIMING
8.6Clock Switching
8.6.3 TIMER1 OSCILLATOR READY (T1OSCR) BIT
8.7Two-Speed Clock Start-up Mode
8.8Fail-Safe Clock Monitor
8.8.1 FAIL-SAFE DETECTION
8.8.2 FAIL-SAFE OPERATION
8.8.3 FAIL-SAFE CONDITION CLEARING
8.8.4 RESET OR WAKE-UP FROM SLEEP
9.0SR LATCH
10.2Code Protection
11.0ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE
11.2ADC Operation
11.2.5SPECIAL EVENT TRIGGER
12.0COMPARATOR MODULE
13.0DIGITAL-TO-ANALOG CONVERTER (DAC) MODULE
13.5Operation During Sleep
Digital-to-Analog Converter (DAC)
14.0FIXED VOLTAGE REFERENCE
15.0TIMER0 MODULE
16.0TIMER1 MODULE WITH GATE CONTROL
16.2Clock Source Selection
17.0TIMER2/4/6 MODULES
17.1Timer2/4/6 Operation
18.0CAPACITIVE SENSING MODULE
REGISTER 18-1:CPSCON0: CAPACITIVE SENSING CONTROL REGISTER 0
REGISTER 18-2:CPSCON1: CAPACITIVE SENSING CONTROL REGISTER 1
19.1Capture/Compare/PWM
19.3.1CCPX PIN CONFIGURATION
19.4.1CCPX PIN CONFIGURATION
19.4.4SPECIAL EVENT TRIGGER
19.5.4OPERATION IN SLEEP MODE
19.5.6EFFECTS OF RESET
19.5.7SETUP FOR PWM OPERATION
19.6.1HALF-BRIDGE MODE
19.6.2FULL-BRIDGE MODE
19.6.3START-UP CONSIDERATIONS
19.6.4ENHANCED PWM AUTO-SHUTDOWN MODE
20.0ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART)
20.1.2.5Receive Overrun Error
20.2Clock Accuracy with Asynchronous Operation
20.3.1AUTO-BAUD DETECT
20.4.1.3Synchronous Master Transmission
21.0LIQUID CRYSTAL DISPLAY (LCD) DRIVER MODULE
21.3LCD Bias Voltage Generation
21.6Segment Enables
21.11Operation During Sleep
22.0MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE
22.5.6CLOCK STRETCHING
22.6.9STOP CONDITION TIMING
FIGURE 22-30: BUS COLLISION DURING START CONDITION (SDA ONLY)
FIGURE 22-32: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
FIGURE 22-33: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
FIGURE 22-34: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
FIGURE 22-36: BUS COLLISION DURING A STOP CONDITION (CASE 2)
23.0DATA EEPROM AND FLASH PROGRAM MEMORY CONTROL
24.0POWER-DOWN MODE (SLEEP)
24.2Wake-up Using Interrupts
25.0IN-CIRCUIT SERIAL PROGRAMMING™ (ICSP™)
26.0INSTRUCTION SET SUMMARY
26.1Read-Modify-Write Operations
27.0DEVELOPMENT SUPPORT
27.1MPLAB Integrated Development Environment Software
27.2MPASM Assembler
27.4MPLINK Object Linker/ MPLIB Object Librarian
27.8MPLAB REAL ICE In-Circuit Emulator System
27.9MPLAB ICD 2 In-Circuit Debugger
27.10MPLAB PM3 Device Programmer
27.11PICSTART Plus Development Programmer
28.0ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings(†)
28.6Thermal Considerations
28.7 Timing Parameter Symbology
30.0PACKAGING INFORMATION
APPENDIX A:DATA SHEET REVISION HISTORY
APPENDIX B:MIGRATING FROM OTHER PIC® DEVICES
INDEX
THE MICROCHIP WEB SITE
CUSTOMER CHANGE NOTIFICATION SERVICE
CUSTOMER SUPPORT
READER RESPONSE
PRODUCT IDENTIFICATION SYSTEM
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Published by: madhuvariar on Sep 14, 2010
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11/22/2012

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