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Table Of Contents

Contents
Introduction to VHDL
1.1 Background
1.2 Event-driven simulation
1.3 Design units
1.3.1 Entity
1.3.2 Architecture
1.3.3 Configuration
1.3.4 Component
1.3.5 Package
1.4 Data types and modelling
1.4.1 Type declaration
1.4.2 Signals
1.4.3 Generics
1.4.4 Constants
1.4.5 Variables
1.4.6 Common operations
1.5. Process statement
1.5 Process statement
1.5.1 Sequential vs. combinatorial logic
1.6. Instantiation and port maps
1.6 Instantiation and port maps
1.7 Generate statements
1.8 Simulation
1.8.1 Testbenches
1.8.2 Modelsim
1.8.3 Non-synthesizable code
1.9 Design example
Design Methodology
2.1 Structured VHDL programming
2.1.1 Source code disposition
2.1.2 Records
2.1.3 Clock and reset signal
2.1.4 Hierarchy
2.1.5 Local variables
2.1.6 Subprograms
2.1.7 Summary
2.2 Example
2.3 Technology independence
2.3.1 ASIC Memories
2.3.2 ASIC Pads
2.3.3 FPGA modules
2.3.4 FPGA Pads
2.3.5 ALU unit
Arithmetic
3.1 Introduction
3.2 VHDL Packages
3.2.1 Data types
3.2.2 Operations
3.2.3 VHDL examples
3.3 DesignWare
3.3.1 Arithmetic Operations using DesignWare
3.3.2 Manual Selection of the Implementation in dc shell
3.4 Addition and Subtraction
3.4.1 Basic VHDL example
3.4.2 Increasing wordlength
3.4.3 Counters
3.4.4 Multioperand addition
3.4.5 Implementations
3.5 Comparison operation
3.5.1 Basic VHDL example
3.6 Multiplication
3.6.1 Multiplication by constants
3.6.2 Multiplication of signed numbers
3.7 Datapath Manipulation
4.1 SR example
4.2. Memory split example
4.2 Memory split example
4.3 Cache example
Synthesis
5.1 Basic concepts
5.2 Setting up libraries for synthesis
5.3 Baseline synthesis flow
5.3.1 Sample synthesis script for a simple design
5.4.2 Constraining the design for better performance
5.4.3 Compile mode concepts
5.4.4 Compile strategy
5.4.5 Design Optimization and constraints
5.4.7 Optimization flow
5.5 Coding style for synthesis
5.5.1 Coding style if statement
5.5.2 Coding style for loop statement
Place & Route
6.1 Introduction and Disclaimer
6.2 Starting Silicon Ensemble
6.3 Import to SE
6.4. Creating a mac file
6.4 Creating a mac file
6.5. Floorplanning
6.5 Floorplanning
6.6. Block and Cell Placement
6.6 Block and Cell Placement
6.7 Power Routing
6.8 Connecting Rings
6.9. Clock Tree Generation
6.9 Clock Tree Generation
6.10. Filler Cells
6.10 Filler Cells
6.11 Clock and Signal Routing
6.12. Verification and Tapeout
6.12 Verification and Tapeout
6.13 Acknowledgements
7.1 Sources of power consumption
7.1.1 Dynamic power consumption
7.1.2 Static power consumption
7.2 Optimization
7.2.1 Architecural issues—Pipelining and parallelization
7.2.2 Clock gating
7.2.3 Operand isolation
7.2.4 Leakage power optimization
7.2.5 Beyond clock gating
7.3 Power estimation with Synopsys Power Com-
7.3.1 Switching Activity Interchange Format (SAIF)
7.3.2 Information provided by the cell library
7.3.3 Calculating the power consumption
7.4 Power-aware design flow at the gate level
7.5 Scripts
7.5.1 Design flow
7.5.2 Patches
7.6 Commands in DC
7.6.1 Some useful DC commands
7.6.2 nc-verilog
7.7 The ALU example
Formal Verification
8.1 Concepts within Formal Verification
8.1.1 Formal Specification
8.1.2 The System Model
8.2. Areas of Use for Formal Verification Tools
8.1.3 Formal Verification
8.1.4 Formal System Construction
8.2 Areas of Use for Formal Verification Tools
8.2.1 Model Checking
8.2.2 Equivalence Checking
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Asic Flow Tutorial

Asic Flow Tutorial

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Published by sleepnomore

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Published by: sleepnomore on Sep 14, 2010
Copyright:Attribution Non-commercial

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/*********** DO NOT ALTER ANYTHING BELOW THIS LINE ! ************/ var s_code=s.t();if(s_code)document.write(s_code)//-->