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Table Of Contents

Component Interconnect (PCI) Bus
So What is a Computer Bus?
Bus Taxonomy
What’s Wrong with ISA and Attempts to Fix It
The VESA Local Bus
Introducing PCI
Features
The PCI Special Interest Group
PCI Signals
Signal Groups
Signal Types
Sideband Signals
Definitions
Summary
The Arbitration Process
An Example of Fairness
Bus Parking
Latency
PCI Bus Commands
Basic Read/Write Transactions
Transaction Termination—Initiator
Transaction Termination—Target
64-bit Extensions
System Management Bus (SMB)
A “Green” Architecture
Signaling Environments—3V and 5V
5 Volt Signaling Environment
3.3 Volt Signaling Environment
Timing Specifications
66 MHz PCI
Mechanical Details
Background
Configuration Address Space
Configuration Header—Type 0
Base Address Registers (BAR) (0x10 to 0x24)
Expansion ROM (0x30)
Capabilities List
Vital Product Data
Bridge Types
Configuration Address Types
Configuration Header—Type 1
Bus Hierarchy and Bus Number Registers
Address Filtering—the Base and Limit Registers
Prefetching and Posting to Improve Performance
Interrupt Handling Across a Bridge
Bridge Support for VGA—Palette “Snooping”
Resource Locking
Who Configures the System?
System Configuration—An Overview
BIOS Services
Introduction—Why CompactPCI?
Mechanical
Electrical
CompactPCI Bridging
PCI Hot Plug
CompactPCI Hot Swap
Why PCI-X
What’s New
Backward Compatibility
PCI-X Transactions
PCI-X Commands
Split Transactions
Error Checking and Correcting
Source Synchronous Data Transfers
Device ID Messages
16-bit Bus
Configuration Transaction Timing
Configuration Address
Configuration Attributes
Configuration Header Registers
PCI-X Capabilities List Item
Mode 2 Configuration Space
Initialization
Signal Categories
Timing Parameters
1.5 Volt Signaling Environment
PCIXCAP and MODE2
Index
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Demys

Demys

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Published by: abhipankaj on Sep 15, 2010
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