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Table Of Contents

1.1 NUMBERING SYSTEMS
1.1.1 A Review of the Decimal System
1.1.2 Binary Numbering System
NUMBERING SYSTEMS
1.1.3 Binary Formats
1.2 DATA ORGANIZATION
1.2.2 Nibbles
1.2.5 Double Words
1.3 OCTAL NUMBERING SYSTEM
1.3.1 Octal to Decimal, Decimal to Octal Conversion
1.3.2 Octal to Binary, Binary to Octal Conversion
1.4 HEXADECIMAL NUMBERING SYSTEM
1.5 RANGE OF NUMBER REPRESENTATION
1.7.2 Subtraction Using 1’s and 2’s Complement
1.7.3 Signed Binary Representation
1.7.4 Arithmetic Overflow
1.7.6 r’s Complement and (r – 1)’s Complement
1.7.7 Rules for Subtraction Using r’s and (r–1)’s Complement
1.8 BINARY CODED DECIMAL (BCD) AND ITS ARITHMETIC
1.9.1 Weighted Binary Codes
1.9.3 Error Detecting Codes
1.9.4 Error Correcting Codes
1.9.5 Hamming Code
1.9.6 Cyclic Codes
1.10 SOLVED EXAMPLES
1.11 EXERCISES
2.0 INTRODUCTORY CONCEPTS OF DIGITAL DESIGN
2.2 AXIOMATIC SYSTEMS AND BOOLEAN ALGEBRA
2.2.1 Huntington’s Postulates
2.2.2 Basic Theorems and Properties of Boolean Algebra
2.3 BOOLEAN FUNCTIONS
2.3.1 Transformation of Boolean Function into Logic Diagram
2.3.2 Complement of a Function
2.4 REPRESENTATION OF BOOLEAN FUNCTIONS
2.4.3 Conversion between Standard Forms
2.5.2 Gate Definition
2.5.3 The AND Gate
2.5.4 The OR Gate
2.5.7 Universal Gates
2.5.10 Extension to Multiple Inputs in Logic Gates
2.7 EXERCISES
3.1 MINIMIZATION USING POSTULATES AND THEOREM OF BOOLEAN ALGEBRA
3.2 MINIMIZATION USING KARNAUGH MAP (K-MAP) METHOD
3.2.1 Two and Three Variable K Map
3.2.3 Minimization in Products of Sums Form
3.2.4 Four Variable K-Map
3.2.5 Prime and Essential Implicants
3.2.6 Don’t care Map Entries
3.2.9 Multi Output Minimization
3.3 MINIMIZATION USING QUINE-MCCLUSKEY (TABULAR) METHOD
3.4 EXERCISES
4.1 ARITHMATIC CIRCUITS
4.1.2 Subtractors
4.1.3 Code Converters
4.2.2 Decoders (Demultiplexers)
4.2.3 Encoders
4.2.4 Serial and Parallel Adders
4.2.5 Decimal Adder
4.2.6. Magnitude Comparator
4.3.1 Hazards in Combinational Circuits
4.3.2 Types of Hazards
4.3.3 Hazard Free Realizations
4.3.4 Essential Hazard
4.3.5 Significance of Hazards
4.4 FAULTDETECTION AND LOCATION
1.Classical method
4.4.1 Classical Method
4.4.2 The Fault Table Method
4.4.3 Fault detection by Path Sensitizing
5.1 READ ONLY MEMORY (ROM)
5.1.1 Realizing Logical Functions with ROM
5.2.1 Realizing Logical Functions with PLAs
5.3 PROGRAMMABLE ARRAY LOGIC (PAL)
5.3.1 Commercially Available SPLDs
5.3.3 Applications of PLDs
5.4 COMPLEX PROGRAMMABLE LOGIC DEVICES (CPLD)
5.4.1 Applications of CPLDs
5.5.1 Applications of FPGAs
5.6 USER-PROGRAMMABLE SWITCH TECHNOLOGIES
5.7EXERCISES
6.1.4 Triggering of Flip Flops
6.1.6 Race Around Condition and Solution
6.1.7 Operating Characteristics of Flip-flops
6.1.8 Flip-Flop Applications
6.2 FLIP FLOP EXCITATION TABLE
6.4 ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
6.5 DESIGN OF CLOCKED SEQUENTIAL CIRCUITS
6.7 SOLVED EXAMPLES
6.8 EXERCISES
7.1 SHIFT REGISTERS
7.2 MODES OF OPERATION
7.3 APPLICATIONS OF SHIFT REGISTERS
7.3.1 To Produce Time Delay
7.3.2 To Simplify Combinational Logic
7.3.3 To Convert Serial Data to Parallel Data
7.4.1 Introduction
7.4.2 Binary Ripple Up-Counter
7.4.3 4-BIT BINARY RIPPLE UP-COUNTER
7.4.4 3-Bit Binary Ripple Down Counter
Fig. 7.16 3-bit binary ripple down counter
7.4.5 Up-Down Counters
7.4.6 Reset and Preset Functions
7.4.7 Universal Synchronous Counter Stage
7.4.8 Synchronous Counter ICs
7.4.9 Modulus Counters
7.4.10 Counter Reset Method (Asynchronous Counters)
7.4.12 Design of Synchronous Counters
7.4.13 Lockout
7.4.14 MSI Counter IC 7490 A
7.4.15 MSI Counter IC 7492A
7.4.16 Ring Counter
7.4.17 Johnson Counter
7.4.18 Ring Counter Applications
7.5EXERCISES
8.1 DIFFERENCE BETWEEN SYNCHRONOUS AND ASYNCHRONOUS
8.2 MODES OF OPERATION
8.3 ANALYSIS OF ASYNCHRONOUS SEQUENTIAL MACHINES
8.3.1 Fundamental Mode Circuits
•Circuits without latches
8.3.2 Circuits without Latches
8.3.3 Transition Table
8.3.4 Flow table
8.3.5 Circuits with Latches
8.3.6 Races and Cycles
8.3.7 Pulse-mode Circuits
8.4 ASYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN
8.4.1 Design Steps
8.4.2 Reduction of States
8.4.3 Merger Diagram
8.5 ESSENTIAL HAZARDS
8.6 HAZARD-FREE REALIZATION USING S-R FLIP-FLOPS
8.7 SOLVED EXAMPLES
8.8 EXERCISES
9.1 DESIGN OF DIGITAL SYSTEM
9.2 THE ELEMENTS AND STRUCTURE OF THE ASM CHART
9.2.1 ASM Block
9.2.2 Register Operation
9.2.3 ASM Charts
9.2.4 MOD-5 Counter
9.3 TIMING CONSIDERATIONS
9.4 DATA PROCESSING UNIT
(a)Data Processing Unit
9.5 CONTROL DESIGN
(i)Multiplexer Controls
9.5.1 Multiplexer Control
9.5.2 PLA Control
10.0 INTRODUCTION
10.1 FUNDAMENTALS OF SEMICONDUCTORS AND SEMICONDUCTOR SWITCHING DEVICES
10.1.1 Semiconductors
10.1.2 Semiconductor Diode or PN Junction
10.1.3 Bipolar Junction Transistor (BJTs)
10.2 CHARACTERISTICS OF LOGIC FAMILIES
10.2.1 Classification of Logic Families
10.2.2 Characteristics of Digital ICs and families
10.3 IMPLEMENTATION OF LOGIC FAMILIES
10.3.1 Basic Diode Logic
10.3.2 Resistor Transistor Logic (RTL)
10.3.3 Direct Coupled Transistor Logic (DCTL)
10.3.4 Diode Transistor Logic (DTL)
10.3.5 High Threshold Logic (HTL)
10.3.6 Transistor Transistor Logic (TTL)
10.3.9 Three State Logic (TSL)
10.4 INTERFACING OF LOGIC GATES
10.4.1 TTL to CMOS Interface
10.4.2 CMOS to TTL Interface
10.5 COMPARISON OF LOGIC FAMILIES
11.0 INTRODUCTION
11.1 MEMORY BASICS
11.2 MEMORY CHARACTERISTICS
11.3 MASS STORAGE DEVICES
11.4 SEMICONDUCTOR MEMORY
11.4.1 Basic Memory Unit
11.4.2 Basic Memory Organization
11.4.3 Cell Organization (Memory Addressing)
11.4.3.1 Matrix Addressing
11.4.4 Organizing Word Lengths (Different Memory Organization)
11.4.5 Classification of Semiconductor Memory
11.4.6 Semiconductor Memory Timing
11.4.6.1 Memory Write Operation
11.4.6.2 Memory Read Operation
11.4.7 Read Only Memory
11.4.7.1 Some Simple ROM Organizations
11.4.7.2 Mask Programmed ROMs
11.4.8 Programmable Read Only Memory (PROM)
11.4.8.1 Bi-Polar PROMs
11.4.8.2 MOS PROMs
11.4.8.3 PROM Programming
11.4.9.1 EPROM Programming
11.4.9.2 The 27XXX EPROM Series
11.4.11 The Random Access Memory (RAM)
11.4.12 Static Random Access Memory (SRAM)
11.4.12.1 The Bi-Polar SRAM Cell
11.4.12.2 The MOS SRAM Cell
11.4.12.3 SRAM ICs
11.4.13 Dynamic Random Access Memory (DRAM)
11.4.13.1 Basic DRAM Cell
11.4.13.2 One MOS Transistor DRAM Cell
11.4.13.3 DRAM Organization
11.4.14 SRAMs and DRAMs
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Copia de Digital Principles Switching Theory - 2006 OK MGB

Copia de Digital Principles Switching Theory - 2006 OK MGB

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Published by: fenixblack on Sep 18, 2010
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