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hdl

hdl

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Published by: kumar0711 on Sep 19, 2010
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12/18/2011

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DEPARTMENTOFELECTRONICS & COMMUNICATION ENGINEERINGECE 452 – VHDL and CAD LABLABORATORY MANUALR.V.R. & J.C. COLLEGE OF ENGINEERING(Approved by AICTE)(Affiliated to Nagajuna University)CHANDRAMOULIPURAM::CHOWDAVARAMGUNTUR – 522 019
 
 
CONTENTS
VHDL modeling and Synthesis of the following Experiments1.
 
Logic Gates2.
 
Modulo-N Synchronous/Asynchronous up down Counters3.
 
Multiplexers/De- Multiplexers4.
 
Design of ALU5.
 
8 to 3 Priority Encoder/ BCD to 7 Segment Decoder 6.
 
4 bit Magnitude Comparator 7.
 
Parity Generator 
 
OBJECTIVES
Active-VHDL is an integrated environment designed for development of VHDL designs. Thecore of the system is a VHDL simulator. Along with debugging and design entry tools, it makesup a complete self-sufficient system that allows you to write, debug and simulate VHDL code.Based on the concept of a design, Active-VHDL allows you to organize your VHDL resourcesinto a convenient and clear structure.
Standards Supported
VHDL
The VHDL simulator implemented in Active-VHDL supports the VHDL-93 language standard.Some language constructs are not supported in this release.
VITAL
The simulator provides built-in acceleration for VITAL packages version 3.0. The VITAL-compliant models can be annotated with timing data from SDF files. SDF files must comply withOVI Standard Delay Format Specification Version 2.1.
AVHDL Command Language
All operations in Active-VHDL can be performed using Active-VHDL command language.Active-VHDL accepts all commands used by Model Technology V-System ™. The commandsthat are inapplicable or not supported in the Active-VHDL environment are also accepted buthave no effect on the operation of the application.
Hardware and Software Requirements
Active-VHDL requires:· A Pentium PC· 32 MB physical memory (64 MB recommended)· Microsoft Windows 95 or Windows NT 4.0 with Service Pack 3 for Windows NT 4.0· A hard disk drive with at least 100 MB spare capacity (for full installation)

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