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Table Of Contents

1 INTRODUCTION
1.1 Overview
1.2 Summary of Contributions
1.2.1 Memory Efficient Decoder for Quasi-Cyclic LDPC Codes
1.2.2 Efficient Design of High Speed LDPC Decoders
1.2.3 Low Complexity Decoding of LDPC Codes
1.2.4 Reducing Iterations for LDPC Codes
2 DECODING OF LDPC CODES
2.1 Introduction of LDPC Codes
2.1.1 Representations of LDPC Codes
2.1.2 LDPC Code Construction and Encoding
2.2 Belief Propagation Decoding Algorithm
2.3 Min-Sum Decoding Algorithms
2.4 BCJR Algorithm Based Decoding Approach
2.5 Bit Flipping and Weighted Bit Flipping Based Algorithms
3.3 The Memory Efficient Decoder Architecture
3.4 Optimization on the Partially Parallel Decoder Architecture
3.4.1 The Optimized CNU
3.4.2 The Optimized Data Scheduling Unit
3.4.3 The Optimized Data Merge Unit
3.5 Summary
4 EFFICIENT VLSI DESIGN OF HIGH THROUGHPUT LDPC DECODERS
4.1 Efficient Message Passing Architecture
4.1.1 Efficient Message Passing Schemes with Min-Sum Algorithm
4.1.2 Architecture for Permuation Matrices Based LDPC Codes
4.1.3 Further Complexity Reduction with Non-uniform Quantization
TABLE 4.1 3-BIT QUANTIZATION FOR RECEIVED SYMBOL
4.2 Layered Decoding Architecture for Quasi-Cyclic Codes
4.2.1 Row Permutation of Parity Check Matrix of QC-LDPC Codes
4.2.2 Approximate Layered Decoding Approach
4.2.3 Decoder Architecture with Layered Decoding Approach
4.2.4 Hardware Requirement and Throughput Estimation
TABLE 4.3 GATE COUNT ESTIMATION FOR COMPUTING BLOCKS
TABLE 4.4 STORAGE REQUIREMENT ESTIMATE
4.3 An FPGA Implementation of Quasi-Cyclic LDPC Decoder
4.3.1 The (8176, 7156) EG-based QC LDPC Code
4.3.2 Partially Parallel Decoder Architecture
4.3.3 Fixed-point implementation
TABLE 4.5. UNIFORM TO NON-UNIFORM QUANTIZATION CONVERSION
4.3.4 FPGA Implementation
TABLE 4.6. XILINX VIRTEXII-6000 FPGA UTILIZATION STATISTICS
4.4 Summary
5 PRACTICAL LOW COMPLEXITY LDPC DECODERS
5.1 The Optimized 2-bit Decoding
5.1.1 Decoding Scheme
TABLE 5.1 DATA CONVERSION FOR THE RATE-0.84 CODE
5.1.2 Decoding Performance Simulation
5.2 Low complexity 2-bit decoder design
5.2.1 Memory Reduction Scheme
TABLE 5.2 MEMORY REQUIREMENT OF THE 2-BIT DECODER
TABLE 5.3 MEMORY REQUIREMENT OF MWBF DECODER
5.2.2 Computation Units Design
WBF-based decoder
5.3 Summary
6 REDUCING ITERATIONS FOR LDPC CODES
6.1 Extended Layered Decoding of LDPC Codes
6.1.2 Overlapped Message Passing Decoding
6.1.3 Simulation Results
6.2 An Efficient Early Stopping Scheme for LDPC Decoding
6.3 The Fast Decoding Scheme for WBF-based Algorithms
6.3.1 Multi-threshold Bit Flipping Scheme
6.3.2 Performance Simulation
6.4 Summary
7 CONCLUSIONS AND FUTURE WORKS
7.1 Conclusions
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Published by: raghu555_k on Sep 23, 2010
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11/01/2011

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/*********** DO NOT ALTER ANYTHING BELOW THIS LINE ! ************/ var s_code=s.t();if(s_code)document.write(s_code)//-->