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Table Of Contents

About the In-Depth Tutorial
Tutorial Contents
Tutorial Flows
•HDL design flow
•Schematic design flow
HDL Design Flow
Schematic Design Flow
Implementation-Only Flow
Additional Resources
•“Software Overview”
Software Overview
Project Navigator Interface
Design Panel
View Pane
Hierarchy Pane
Processes Pane
Files Panel
Libraries Panel
Console Panel
Errors Panel
Warnings Panel
Error Navigation to Source
Error Navigation to Answer Record
Design Summary/Report Viewer
Using Project Revision Management Features
Understanding the ISE Project File
Making a Copy of a Project
Using the Project Browser
Using Project Archives
Creating an Archive
Restoring an Archive
HDL-Based Design
•“Overview of HDL-Based Design”
•“Getting Started”
Overview of HDL-Based Design
Getting Started
Required Software
Optional Software Requirements
VHDL or Verilog
Installing the Tutorial Project Files
Starting the ISE Software
Creating a New Project
Stopping the Tutorial
Design Description
Functional Blocks
Design Entry
Adding Source Files
Correcting HDL Errors
Creating an HDL-Based Module
Using the New Source Wizard and ISE Text Editor
Using the Language Templates
Adding a Language Template to a File
Creating a CORE Generator Software Module
Creating the timer_preset CORE Generator Software Module
Instantiating the CORE Generator Software Module in the HDL Code
Creating a DCM Module
Using the Clocking Wizard
Instantiating the dcm1 Macro—VHDL Design
Instantiating the dcm1 Macro—Verilog
Synthesizing the Design
Synthesizing the Design Using XST
Entering Synthesis Options
Using the RTL/Technology Viewer
Synthesizing the Design Using Synplify/Synplify Pro Software
Entering Synthesis Options and Synthesizing the Design
Examining Synthesis Results
•“Compiler Report”
Compiler Report
Resource Utilization
Synthesizing the Design Using Precision Synthesis
Schematic-Based Design
•“Overview of Schematic-Based Design”
Overview of Schematic-Based Design
Opening the Schematic File in the Xilinx Schematic Editor
Manipulating the Window View
Creating a Schematic-Based Macro
Defining the time_cnt Schematic
Adding I/O Markers
Adding Schematic Components
Correcting Mistakes
Drawing Wires
Adding Buses
Adding Bus Taps
Adding Net Names
Checking the Schematic
Saving the Schematic
Creating and Placing the time_cnt Symbol
Creating the time_cnt Symbol
Placing the time_cnt Symbol
Creating the dcm1 Symbol
Creating Schematic Symbols for HDL Modules
Changing Instance Names
Using Hierarchy Push/Pop
Specifying Device Inputs/Outputs
Adding Input Pins
Adding I/O Markers and Net Names
Completing the Schematic
Behavioral Simulation
•“Overview of Behavioral Simulation Flow”
•“ModelSim Setup”
Overview of Behavioral Simulation Flow
ModelSim Setup
ModelSim PE, SE, and DE
ModelSim Xilinx Edition
ISim Setup
Required Files
Design Files (VHDL, Verilog, or Schematic)
Test Bench File
Simulation Libraries
Xilinx Simulation Libraries
Updating the Xilinx Simulation Libraries
Mapping Simulation Libraries in the modelsim.ini File
Adding an HDL Test Bench
Adding the Tutorial Test Bench File
VHDL Simulation
Verilog Simulation
Behavioral Simulation Using ModelSim
Locating the Simulation Processes
Specifying Simulation Properties
Performing Simulation
Adding Signals
Adding Dividers
Analyzing the Signals
Saving the Simulation
Behavioral Simulation Using ISim
Rerunning Simulation
Design Implementation
•“Overview of Design Implementation”
Overview of Design Implementation
Continuing from Design Entry
Starting from Design Implementation
Specifying Options
Creating Timing Constraints
Translating the Design
Using the Constraints Editor
Assigning I/O Locations Using PlanAhead Software
Mapping the Design
Using Timing Analysis to Evaluate Block Delays After Mapping
Estimating Timing Goals with the 50/50 Rule
Reviewing the Post-Map Static Timing Report
Placing and Routing the Design
Using FPGA Editor to Verify the Place and Route
Evaluating Post-Layout Timing
•View the Post-Place and Route Static Timing Report
Viewing the Post-Place and Route Static Timing Report
Analyzing the Design using the PlanAhead Software
Creating Configuration Data
Creating a PROM File with iMPACT
Command Line Implementation
Timing Simulation
•“Overview of Timing Simulation Flow”
Overview of Timing Simulation Flow
Specifying a Simulator
Timing Simulation Using ModelSim
Specifying Simulation Process Properties
Timing Simulation Using Xilinx ISim
Viewing Full Signal Names
iMPACT Tutorial
•“Device Support”
•“Download Cable Support”
Device Support
Download Cable Support
Parallel Cable IV
Platform Cable USB
Platform Cable USB-II
Configuration Mode Support
Generating the Configuration Files
Connecting the Cable
Starting the Software
Opening iMPACT from Project Navigator
Opening iMPACT Standalone
Creating an iMPACT New Project File
Using Boundary-Scan Configuration Mode
Specifying Boundary-Scan Configuration Mode
Assigning Configuration Files
Saving the Project File
Editing Preferences
Performing Boundary-Scan Operations
Troubleshooting Boundary-Scan Configuration
Verifying the Cable Connection
Verifying the Chain Setup
Creating an SVF File
Setting Up the Boundary-Scan Chain
Setting Up the JTAG Chain for SVF Generation
Manually Setting Up the JTAG Chain for SVF Generation
Writing to the SVF File
Stopping Writing to the SVF File
Playing Back the SVF or XSVF File
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Ise Tutorial Ug695

Ise Tutorial Ug695

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Published by vinai2086

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Published by: vinai2086 on Oct 02, 2010
Copyright:Attribution Non-commercial


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