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IRQ -ordinateur

IRQ -ordinateur

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Published by FOUAD EL BRAHMI

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Published by: FOUAD EL BRAHMI on Jul 10, 2008
Copyright:Public Domain

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11/08/2012

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I
n the course of normal operations, the various I/O devices attached to a PC, such as thekeyboard and disk drives, require servicing from the system’s microprocessor. AlthoughI/O devices may be treated like memory locations, there is one big difference between thetwo:I/Odevicesgenerallyhavethecapabilitytointerruptthemicroprocessorwhileitisexe-cutingaprogram.TheI/Odevicedoesthisbyissuingan
Interrupt
(
INT
)or 
InterruptRe-quest
(
INTR or IRQ
) input signal to the microprocessor.
INTERRUPTS
IfthemicroprocessorisrespondingtoINTsignalsandaperipheraldeviceissuesaninterruptrequest on an IRQ line, the microprocessor will finish executing its current instruction andissue an
Interrupt Acknowledge
(
INTA
) signal on the control bus. The microprocessor suspendsitsnormaloperationandstoresthecontentsofitsinternalregistersinaspecialstor-age area referred to as the
stack 
.The interrupting device (or an interrupt controller) responds by sending the starting addressofaspecialprogramcalledthe
interruptserviceroutine
tothemicroprocessor.Themicro- processor uses the interrupt service routine to service the interrupting device. After the mi-croprocessorfinishesservicingtheinterruptingdevice,thecontentsofthestackarerestoredtotheiroriginallocations,andthemicroprocessorreturnstotheoriginalprogramatthepointwhere the interrupt occurred.Becausemorethanoneperipheraldevicemightrequiretheattentionofthemicroprocessoratanygiventime,allcomputersystemshavemethodsofhandlingmultipleinterruptsinanor-derly fashion. The simplest method calls for the microprocessor, or the interrupt controller,tohavemultipleinterruptinputsthathaveafixedpriorityofservice.Inthismanner,iftwoin-terruptsignalsoccuratthesameinstant,theinterruptthathasthehighestpriorityisservicedfirst.Actually, there are two varieties of interrupts used in microcomputers:
·
Maskable interrupts
(
MI
)—which can be ignored under certain conditions
·
Non-maskable interrupts
(
NMI
)—which it must always respond to
HOW INTERRUPTS WORK 1
INTRODUCTION
H
OW 
I
NTERRUPTS
ORK 
 
Mostmicroprocessorshaveanoutputlinecalledthe
InterruptEnable
(
INTE
)thatitusestoinform peripheral devices whether it can be interrupted. The logic level present on this linedetermineswhetherthemicroprocessorwillrespondtoanINTorIRQinputsignal.Thecon-ditionoftheINTElinecanusuallybecontrolledbysoftware,whichmeanstheprogramcandetermine whether the interrupt operation will be activated. Non-maskableinterrupt inputs,ontheotherhand,aresignalsthatcannotbeignoredbythemicroprocessorand,therefore,al-ways cause an interrupt to occur regardless of the status of the INTE line.A programmable interrupt controller IC and its relationship to the system’s microprocessor is illustrated in Figure 1. The interrupt controller chip in the figure accepts prioritized IRQsignalsfromuptoeightperipheraldevicesonIRQlines0through7.Whenoneoftheperiph-erals desires to communicate with the microprocessor, it sends an IRQ to the interrupt con-troller. The controller responds by sending an INT signal to the microprocessor. If twointerrupt requests are received at the same instance, the interrupt controller accepts the onethathasthehigherpriorityandactsonitfirst.Thepriorityorderishighestforthedevicecon-nectedtotheIRQ-0lineanddescends inorder,withtheIRQ-7inputgiventhelowestprior-ity.
Interrupt Circuitry
Inthecourseofnormaloperations,thevariousI/OdevicesattachedtotheTurbo-PC—suchas the keyboard and disk drives—require servicing from the system’s microprocessor. TheTurbo-PC is an interrupt-driven system and employs the interrupt controller subsystem of the M1523 to ensure quick, smooth performance from the system. Its interrupt subsystem provides 14, independently programmable, edge-triggered, or level-triggered interruptchannels.
HOW INTERRUPTS WORK 2
Figure 1:Programmable Interrupt
 
TheM1523providestwo,8-lineinterruptcontrollers(
INTC1
and
INTC2
),eachofwhichisequivalent to the 8259 PIC (Programmable Interrupt Controller) used in the original PC’s,XT’s, and AT’s. These interrupt controllers are internally cascaded together to provide the16interruptchannelsnecessaryforAT-compatibility.Likethosediscrete8259’susedintheoriginal AT, the M1523’s controllers must be programmed to operate in
cascade mode
.INTC1 is located at hex addresses 020 and 021 while INTC2 is located at 0A0 and 0A1.Figure 2 shows the internal structure of an 8259A Interrupt Controller. It can handle 8active-high,prioritizedinputsignalsoninterruptrequestlinesIRQ-0throughIRQ-7.IRQ-0receives the highest priority while IRQ-7 receives the lowest priority. Interrupt signals ontheselinesarehandledbythe
InterruptRequestRegister
(
IRR 
)whichstoresallofthein-terruptlevelsrequestingservice,andthe
In-ServiceRegister
(
ISR 
)whichstoresthepriorityof all the interrupt levels currently being serviced.
HOW INTERRUPTS WORK 3
Figure 2: Internal Structure of an 8259A Interrupt Controller IC

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/*********** DO NOT ALTER ANYTHING BELOW THIS LINE ! ************/ var s_code=s.t();if(s_code)document.write(s_code)//-->