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Efficient Mapping of Heuristic Packet

Classifier on Network Processor based
Router to enhance QoS for Multimedia
Applications
R. Avudaiammal, P. Seethalakshmi
Research Scholar, Professor,
Anna University Tiruchirappalli

Abstract— Packet classification is an important function performed by network devices such as edge router, firewalls and intrusion detec-

tion systems to provide QoS and network security. With its complexity, the exponential growth of link speed and diversified services offered by

the Internet, Packet classification is becoming a major bottleneck in the router performance. Traditional router performs this classification

using Application Specific Integrated Circuits (ASICs), which suffers from lack of flexibility. Powerful Embedded Network Processor (NPs) a

flexible and cost efficient network appliance has been introduced by many companies that can be an alternative to implement the packet

classification at nearly link speed. The objective of this paper is to design and implement a new low complexity packet classification algorithm

of heuristic type named Trie based Tuple Space Search (TTSS) and to efficiently map this Packet classifier component on Network Proces-

sor based router. The performance is evaluated using Intel’s IXP2400 NP Simulator. The results demonstrate that, TTSS outperforms the

other heuristic packet classification algorithms. Parallel mapping of TTSS on Network processor based router gives better performance than

its pipelined mapping which is more suitable to enhance QoS for multimedia applications.

Index Terms — Multimedia, QoS, Packet Classification, TTSS, Network Processor, and IXP 2400.

1 INTRODUCTION

I nternet traffic has become high in recent times due to

the growth of real-time multimedia applications such
as Video on demand , Video telephony, Video stream-
ing and e-learning that require guaranteed QoS.
Processing of the packets at router level such as Receiving
IP packets from incoming links, classifying the packets,
Scheduling, Routing and output porting are to be per-
formed at high speed to satisfy the QoS requirements.
Packet classification is an important function performed
by network devices such as edge router, firewalls and
intrusion detection systems to provide QoS and network
security. The packets that arrive at the input port of the
router are classified into different flows by a classifier, by
comparing the fields in the L3 / L4 header of the incom-
ing packet. Flow is a sequence of packets that belong to
the same logical stream and should be treated similarly
by the network. A set of rules named as Filters (F) having
the attributes of the packets such as Source IP, Destina-
tion IP are stored as fields in the router table for the pur-
pose of classifying the incoming packets. The classifier
extracts relevant fields from the header of the incoming
packet in the order same as in the Filter to perform multi-
dimensional Packet Classification algorithm. Packet Clas-
sification is carried out by considering the source and
destination address, protocol type of L3 and source port
and destination port of L4. This classification of packets
involves complex tasks such as Longest Prefix Matching
(LPM) for source and destination address, Exact Matching
(EM) for protocol and Range Matching (RM) for port.
With large matching conditions, the best matching rule
based on filters is chosen. In addition to this complex
task, the packet classification has to be done at wire speed
which is a bottleneck at routers.
Currently, Routers are mainly based on Applica-
tion Specific Integrated Circuits (ASICs) that are custom
made and are not flexible to support diversified Internet-
working services. Earlier General Purpose Processor
(GPP) based routers offer flexibility in supporting new
features by simply upgrading the software, but has diffi-
culties in supporting higher bandwidth [1]. Embedded
Network Processors have recently emerged to provide
both the performance of ASICs and the programmability
of GPPs [2]. Powerful Embedded Network Processors
have been introduced by many companies that can be
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placed in routers to execute various network related tasks
at packet level. The design and development of routers
using Network Processor has gained significance due to
its high performance.
Network Processors (NPs) have a high-
performance parallel processing architecture on a single
chip which is more suitable for detailed packet inspection,
processing having complex algorithms and forwarding at
wire speed. Network Processors have a set of hierarchi-
cally distributed memory devices, a set of on-chip proces-
sors (Micro Engines) to carry out packet level parallel
processing operations through multitasking and multith-
readed programming [16]. Each Micro Engine (ME) has
multiple hardware thread contexts that enable thread
context switches with zero or minimal overhead [3]. Mi-
cro Engines can examine and forward packets indepen-
dently without using the host processor, bus, or memory.
All these features reveal that, Micro Engines in the Net-
work Processor can be assigned different packet
processing functionalities so that classification of packets
can be done efficiently to provide QoS. Studies [16-19]
have focused on implementing the networking services
using programmable network processors.
The work presented in this paper is based on the
fully programmable Intel ® IXP 2400 processor. The In-
tel® IXP2400 is a member of the Intel’s second generation
network processor family. The architecture of this inte-
grated network processor IXP2400 [4] shown in Figure 1
has a single 32-bit XScale core processor, eight 32-bit Mi-
croEngines (MEs) organized as two clusters, standard
memory interfaces and high speed bus interfaces. Each
ME has eight hardware-assisted threads and 4KB local
memory. Each microengine has 256 general purpose reg-
isters that are equally shared between eight threads. Mi-
croengines exchange information by using either an on-
chip scratchpad memory or 128 special purpose next
neighbor registers. Data transferring across the MEs and
locations external to the ME, (for eg DRAMs, SRAMs etc.)
are done by using 512 Transfer Registers. The Xscale core
is responsible for initializing and managing the chip,
handling control and management functions and loading
the ME instructions.
IXP2400 chip has a pair of buffers (BUF), Receive
BUF (RBUF) and Transmit BUF (TBUF) that are used to
send / receive packets to / from the network ports with
each of size 8 Kbytes. The packets are injected into the
Network Processor from the network through the Media
Switch Fabric Interface and then forwarded to the Micro-
Engines for processing. All threads in a particular ME
execute program code called microblock stored in the
local memory of that ME. Finally the processed packets
are driven into the network by Media Switch Fabric Inter-
face (MSF) at output port.
In this work, the heuristic Packet clas-
sifier named Trie based Tuple Space Search(TTSS) has
been proposed and implemented on the IXP 2400 Proces-
sor with two supporting microblocks namely Packet Re-
ceive and Packet Transmit. In the router, packet arrival
and departure can occur simultaneously; hence to utilize
the parallel processing of Network processor effectively,
108
the microblocks are arranged in a pipeline. For example,
when the arrival of a new packet is being handled by a
receive microengine, an existing packet can be classified
and transmitted by the respective microblocks simulta-
neously, which entails interaction between microblocks in
the form of pipeline. Also the impact of different design
mappings namely parallel and pipelined mapping of the
packet classification on the Microengines has been ex-
amined and the performance measures show that the pa-
rallel design mapping of Microengines has better packet
processing rate than the pipelined mapping.
The remainder of this paper is organized as fol-
lows: Section 2 presents the background concept of packet
classification. Section 3 and 4 describes the proposed
packet classification algorithm and its implementation
details. The performance analysis is presented in section 5
and conclusion in Section 6.
Figure 1. Architecture of IXP2400
2 RELATED WORK
T his section presents a brief overview of the Packet
Classification algorithms. Survey on packet classifica-
tion algorithms [5], [6], [7] and [8] shows that the
Packet Classification problem is inherently hard. Linear
search is the simplest method of packet classification that
uses linked list to perform searching through a set of
rules. If ‘N’ is the number of rules, then its spatial and
temporal complexity is O (N). Tuple Space (TS), a heuris-
tic for packet classification [9] maps the set of rules to a
Tuple that is stored in a Hash table. As the number of
distinct Tuples is much lesser than the number of rules,
even a simple linear search in the Tuple Space provides a
significant increase in speed of packet classification. It has
the time complexity reduced with order O (Wk) where W
is the length of the IP prefix and ‘k’ is the number of fields
used in classification. Another search namely Pruned
Tuple Space Search (PTS) [10] has the time complexity
reduced further by performing searches on the subset of
the Tuples. Though any field or combination of fields
may be used for pruning, it is found that pruning on
source and destination address strikes a favorable balance
between the reduction in number of Tuples and overhead
for the pruning steps. Tuple-pruning algorithm is able to
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achieve good performance in practical environment:
however its worst-case speed is not guaranteed. Trie
search is another most popular high speed IP route look-
up scheme for packet classification that uses Tree data
Structure with individual bit look-up[11].
Some of the trie-based algorithms follow the hie-
rarchical approach of the packet classification which re-
cursively performs search in each field. In [12-15], trie
based classification algorithm suitable for high speed two
dimensional packet classifications have been described. A
one-dimensional 1-bit trie is a binary tree like structure,
in which each node has two element fields, le(the left
element) and re (the right element), and each element
field has the components child and data. Branching is
done based on the bits in the search key. If the ith bit of the
search key is 0, then at level i child branch followed at a
node is from left-element (the root is at level 0); other-
wise, from right element. In One-Dimensional Multibit
Tries the branching is based on the number of bits known
as “stride”. Multi Dimensional Multibit Trie (MDMT)
search [13-15] is a Trie Search where the packets are clas-
sified by searching the Destination Trie, Source Trie, Pro-
tocol Trie and Port Trie at different levels using stride. It
has time complexity O (W/L) and space complexity O (N
(W/L) 2(k-1)), where ‘L’ is the average length of strides.
Though there are several algorithms specialized for the
case of rules on two fields (e.g. Source and destination IP
address only), it is necessary to design a packet classifica-
tion algorithm that uses more number of header fields to
provide support for diversified services with the re-
quirement of both low memory space and low access
overhead[21]. A new low complexity Trie Based Tuple
Space Search (TTSS) Packet classification algorithm has
been proposed to give a remarkable enhancement to the
existing Trie based and Tuple based algorithms to sup-
port QoS of multimedia applications.
3 TRIE BASED TUPLE SPACE SEARCH
ALGORITHM
T his section presents the proposed TTSS packet classi-
fication algorithm that accelerates the lookup time.
This is achieved by simplifying the lookup procedure
and avoiding unnecessary tuple probing. It is achieved by
dividing the Tuple space into multiple subspaces. Since
each rule is having two major components called an ap-
plication specification and an address prefix pair, classifi-
cation is done in two stages namely: Application field
look up and prefix-pair look up respectively. This appli-
cation specification identifies a specific application ses-
sion by transport protocol, source port and destination
port. Address prefix pair identifies the communicating
subnets by specifying a source address prefix and a desti-
nation address prefix or address prefix pair. The imple-
mentation of the TTSS classifier includes IP destina-
tion/source address, Source/destination port and proto-
col as filter/rule fields. TTSS uses hierarchical trie struc-
ture to store the rules and traverses a trie through a set of
rules for classifying each incoming packet. In TTSS, Exact
109
Matching is carried out at first level for Protocol and Pre-
fix Matching is carried out at the next level for the IP ad-
dress.
Taylor and Turner have given useful characteris-
tics of the filter [22], by analyzing rule sets provided by
ISPs, network equipment vendor, and other researchers
working in the field to verify and compare the perfor-
mance of the proposed classification algorithms. From
[22] it is observed that even though the transport-layer
fields have a wide variety of specifications, the most
common are TCP (49%), followed by UDP (27%), the
wildcard (13%), ICMP (10%) and the other protocols such
as OSPF, IGMP, etc are lesser than 1% of the filters. Be-
cause of the small number of protocol types, node of the
trie at level 1 splits the rule set based on the protocol field
of the header that reduces the number of rules to be
searched to 50% at the next level of the trie. The sample
rule table and the associated data structure of TTSS are
shown in Figure 2.
Moreover the speed and efficiency of several
longest prefix matching and packet processing algorithms
depend upon the number of unique prefix lengths and
the distribution of rules across those unique values. A
majority of the rule sets specify fewer than 15 unique pre-
fix lengths for either source or destination address prefix-
es [16]. The number of unique source/destination prefix
pair lengths is generally lesser than 32, which is smaller
compared to the filter size and 8% of the rules are redun-
dant. According to classic IP addressing structure, in [11]
it has been shown that most of the rules ignore subnet-
ting.
Based on these observations [16] and [22], each
node of the trie at level 2 has been constructed with mul-
tiple elements referring hash tables of prefix pair and pre-
fix length to further reduce the lookup time by reducing
the search space. A node with prefix length ‘w’ has 2w
element fields. All matching candidate rules are identified
by using the destination prefix length ‘w’ as a search key
and for those candidates, rules are further filtered using
the source prefix field. Left most element of the node has
the hash table with prefix length ‘i’ and the hash tables of
other elements will have the rules with prefix length ‘j’,
and the hash tables always satisfy the inequality i > j.
Longest Prefix matching (LPM) is preferred for Address
lookup and hence Packet classification has been per-
formed by traversing the trie from left to right and from
top to bottom using the tuple to reduce the time complex-
ity. This technique drives the algorithm to have the space
and time complexity as O (N) and as (log W) respectively.
With this low complexity, TTSS could be effective for
high speed classification compared to other Multidimen-
sional Multibit Trie (MDMT) packet classification algo-
rithms [11-15].
In this paper, TTSS algorithm has been imple-
mented on the IXP 2400 Network processor platform be-
cause the algorithm is feasible for parallel implementa-
tion. Also the achievement of its performance improve-
ment such as throughput and packet classification rate on
the IXP 2400 with different design mappings (parallel and
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Table 1 Sample rule table

Rule D.A prefix S.A Protocol Port

prefix
R1 1000000* 1010* TCP HTTP
R2 10010* 11010* TCP HTTP
R3 101001* 1010* UDP RTSP
R4 1000101* 010* TCP FTP
R5 110000* 1101* UDP SNMP
R6 111001* 1001* IGMP HTTP
R7 110011* 1100* GRE DNS
R8 1000110* 11011* UDP DNS
Figure 2 Data structure of HASPC
R9 110000* 1101* TCP FTP
R10 1000110* 1100* TCP HTTP
R11 10110* 1000* UDP RTSP
R12 10011* 010* TCP HTTP 4 IMPLEMENTATION
R13
R14
1001000*
101000*
0010*
0010*
UDP
TCP
RTP
FTP
T his section presents the implementation details of
TTSS Packet classification on Intel’s IXP 2400 Net-
work Processor. The implementation architecture is
shown in Figure 3. It consists of modules for Packet Re-
R15 1000100* 0010* UDP RTP ceive, Packet Classification and Packet Transmit. Also
R16 1010000* 1001* * SMTP Layer 2 de-capsulation and header validation are in-
cluded in the Packet Classification module.
R17 101000* 0010* UDP RTP
Packet Receive Microengine has been interfaced
R18 1000100* 0011* TCP FTP
with the Media Switch Fabric Interface (MSF). The pack-
R19 10101* 1101* UDP RTP ets are injected through Media switch Fabric Interface and
Receive Buffer (RBUF). For each packet, the packet data is
R20 10001* 0010* TCP FTP
written to DRAM, the packet meta-data (offset, size) is
R21 100000* 101* TCP FTP written to SRAM. The Receive Process is executed by mi-
croengine (ME0) using all the eight threads available in
R22 101001* 1010* TCP HTTP that microengine (ME0). The packet sequencing is main-
R23 111000* 10001* * SMTP tained by executing the threads in strict order. The packet
buffer information is written to a scratch ring for use by
R24 1001010* 1101* UDP HTTP the packet processing stage Communication between
pipeline stages is implemented through controlled access
R25 10100* 0100* UDP RTSP
to shared ring buffers.
R26 10100* 0101* TCP DLS Classifier microblock is executed by microengine (ME1)
that stores all rules in SRAM as a hierarchical trie data
R27 100001* 010* TCP DNS structure. The classifier micro block does not operate on
R28 1010010* 1010* * SMTP shared data structures and hence inter-thread synchroni-
zation is not needed. The micro block is organized as a
R29 10000* 1011* TCP FTP functional pipe-stage i.e all threads in a microengine ex-
ecutes the same algorithm but they process different
R30 1000101* 010* UDP SNMP
packets.
R31 1000001* 1101* TCP FTP Each rule is associated with QoS information class_id.
This microblock removes the layer-3 header of each in-
R32 1001011* 0010* IGP DNS
coming packet from DRAM by updating the offset and
size fields in the packet Meta using standard protocol
Pipelined design mapping) are evaluated to prove its libraries of IXP 2400. Since it is important to maintain
support of enhancing the QoS for multimedia applica- packet sequencing, the threads in the microblock execute
tions. in strict order to dequeue the packet header from the
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DRAM for performing packet classification. Packet clas-
sifier validates the IP header of esch incoming packet
based on RFC 1812[5]. If the validity check fails, then the
packet is dropped. Otherwise, the packet is classified into
different traffic flows based on the IP header and is en-
queued in the respective queue using the proposed pack-
et classification algorithm. For each valid packet, the mi-
cro block then builds a hash input from the header and
then compares IP header fields with the rule stored in the
hash entry. If a matching entry is found then the classifier
writes selected dispatch loop variables with data stored in
a hash entry and enqueues the packet in the queue ac-
cording to class_id field of the rule for further processing
by the router. Otherwise, if matching fails the algorithm
loads the next hash entry in a chain as indicated by
next_entry_ptr and repeats the entry matching procedure.
If a classifier reaches end of chain without finding a
matching entry, a default rule is applied.
Then the Packet Transmit microblock is executed
by microengine (ME3) that moves packet into TBUFs for
transmitting over the media interface through different
ports. The MSF is monitored by the packet Transmitter
microblock to stop the transmission on that port if the
TBUF threshold for specific ports has been exceeded and
if so it queues up the requests to transmit packets on that
port in local memory. The Packet Transmitter microblock
periodically updates the classifier with information about
how many packets have been transmitted.
and destination addresses and exact match is used for
protocol flag.
5.1 Design Mappings
The implementation of the classification phase on
the IXP2400 can be done in different ways namely parallel
mapping and pipeline mapping. In both the cases, Pack-
et Rx and Packet Tx are processed by microengine 0
(ME0) and microengine 3 (ME3) and the microengines
ME1 and ME2 are used for classification purpose. In pa-
rallel mapping, all the classification steps for a single
packet are processed by the single microengine and hence
ME1 and ME2 perform the classification of different
packets simultaneously.
In pipelined mapping, the classification of a single packet
is done by two different micro engines. ME1 and ME2,
one is for Field Extraction and the other is for Header va-
lidation (according to RFC1812 [5]) and for table lookup.
RX RX
PC
PC PC
PC

4.1 Implementation Environment

IXA 3.51 SDK is a cycle based simulator [18] in
which IXP2400 is set to run under the following condi-
tions: PLL output frequency: 1200 MHz, ME frequency:
600 MHz, Xscale Frequency: 600 MHz. SRAM frequen-
cies: 200 MHz, two channels, 64 MB per channel, DRAM
Frequency: 150 MHz, 64 MB. The configuration for the
device type is x32 MPHY4 with bus mode 1x32 to send
and receive packets from the simulator. A device with 4
ports, each with a data rate of 1000 Mbps and receive and
transmit buffer sizes of 128KB chosen for this application.
The simulator is configured to send packet streams to
ports 0 through 3 of the device. Implementation assigns
individual blocks from the fast path pipeline to separate
microengines on the IXP2400 NPs.
TX TX
Figure 4. Parallel and Pipelined Mapping
The four (LS, TSS, PTS and TTSS) algorithms are
implemented using single microengine, parallel and pipe-
lined design mapping as shown in Figure 4. Figure 5
shows that at the end of 60,000 microengine cycles,
Throughput using TSS is 34.15% more than LS, using PTS
is 67.85% more than LS and it is 73.5% more in TTSS.
Throughput in TTSS is 59.8% and 17.6% more than TSS
and PTS respectively.

Traffic generated in this work includes uniformly

T H R OU GH P U T
120
distributed RTP/UDP packets, UDP packets, TCP pack- 100
ets, etc and all types of classIP addresses.. Traffic is gen- 80
erated with a constant rate of 1000Mb/s and inter-packet 60
gap is set to 96 ns. 40

20

0
5 PERFORMANCE EVALUATION 20000 40000 60000

Simulat ion t ime (cycles)

I n order to evaluate the performance of the algorithm, 5- LS TSS PTS TTSS

tuple header field consisting of IP source and destina-

tion address, protocol type, source and destination
ports is considered because these five fields are common Figure 5 Throughput
fields under literature even though higher number of
fields is possible [11]. Prefix match is used for IP source TTSS outperforms the LS, TSS and PTS based
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packet classification algorithms and hence the perfor- This is due to the fact that in pipelined mapping, a new
mance of the different design mappings is analyzed with packet cannot be handled by microengines earlier in the
TTSS classification algorithm and is shown in Figure 6. pipeline until the availability of inter-microengine buffer
entries. These entries are available only when the entire
T H R O UG H P UT
processing for that packet is completed by all microen-
250
200
gines.
150
P A C KE T S E N T / R E C E IV E R A T IO
100
50
1.2
0 1
LS TSS P TS TTSS 0.8
A lgo rithms 0.6
0.4
P ipelined M apping P arallel M apping
0.2
0
LS TSS PTS TTSS
Figure 6 Throughput Packet Classification Algorithms

P arallel M apping P ipelined M apping

Table 2 Comparison of Performance parameters

Figure 7 Packet Sent/Receive Ratio

I D LE T I M E ( M E 2 )
90
80
70
60
50
40
30
20
10
0
LS TSS PTS TTSS
A lgorit hms

Pipelined M apping Parallel M apping

Figure 8 Idle Time of ME2

Table 2 shows that the speedup factor [20] of
TTSS in parallel mapping is 2.18 and in pipelined map- 12 0
I D LE T I M E ( M E 3 )

ping is 1.52 compared to TTSS classification using single 10 0

microengine. From the table it is also inferred that classi- 80

60
fication rate in TTSS is 2788 KPPS (Kilo Packets per Sec) 40
and 1937 KPPS in parallel and pipelined mapping respec- 20
tivelyThe pipelined mapping seems to be an ideal map- 0
LS TSS PTS TTSS
ping for the algorithm, in which the various steps in
A lg orit hms
processing a packet has been split and assigned across Pip elined M ap ping Parallel M ap ping
microengines. However, the packet processing speed of
TTSS is reduced by 31.25% in pipelined mapping than in
parallel mapping as shown in Figure 7. This is due to the
fact that the access of SRAM occurs only once in parallel Figure 8 Idle Time of ME3
mapping to read the packet header whereas in pipelined
mapping it occurs more than once for a single packet. On analysis, it is seen that Trie based Tuple Space
Microengine being the most important resource Search achieves high speed packet classification using
of NP, its utilization factor can be described by its idle Embedded Network Processor in parallel mapping.
time as shown in Figure 8a. and 8b. In TTSS Idle time of
ME2 is almost 25% lesser than in other algorithms and for
6 CONCLUSION
ME3 it is 32% lesser. The packet classifier in pipelined
mapping exhibits more idle time than that in parallel
mapping. It is clear from Figure 7a and 7b that the idle
time in ME2 and ME3 in Parallel mapping is 21% and
N etwork devices such as edge router, firewalls and
intrusion detection systems devices can utilize pro-
grammable Network Processors (NP) to implement
32% lesser than that of pipelined mapping respectively. a computationally intensive packet classification algo-
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rithm at line speeds to provide QoS and Network securi-
ty. This paper describes the design of Packet Classifier
component on Network based Router and its perfor-
mance enhancement. The proposed low complexity heu-
ristic Trie based Tuple Space Search (TTSS) packet classi-
fication has been implemented on Intel’s IXP 2400 Net-
work Processor to improve the performance of Router.
By dividing the tuple space into multiple subspaces, the
space complexity and the time complexity achieved by
TTSS is O (N) and O (log W) respectively. The implemen-
tation results lead to the observation that Throughput of
Trie based Tuple Space search (TTSS) is almost 60% more,
compared to TSS and PTS. In this work, the performance
of TTSS is also evaluated using pipelined as well as paral-
lel design mapping. The results show that the speedup
factor of TTSS in parallel mapping is 2.18 and in pipelined
mapping is 1.52 compared to TTSS classification using
single microengine. Results prove that classification rate
in TTSS is 2788 KPPS (Kilo Packets per Sec) and 1937
KPPS in parallel and pipelined mapping respectively.
Moreover, the pipelined design mapping has a packet
processing rate of 31.25% lesser than the parallel map-
ping, primarily due to multiple memory reads per packet
in the latter. As compared with the pipelined mapping,
parallel mapping of TTSS classifier can provide higher
Throughput and classification rate. Thus the work sug-
gests that TTSS based packet classification in parallel
mapping is efficient for enhancing QoS of multimedia
applications.
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Mrs. R. Avudaiammal has received her
B.E. degree in Electronics and Communication Engineering from
Madurai Kamaraj University, India in 1992 and M.E. degree in Ap-
plied Electronics from Bharathiar University, India in 2000. She is an
Associate Professor at St.Joseph’s College of Engineering, Chennai,
India. She has 17 years of teaching experience. She has published
books on Microprocessors with Dhanpatrai publication and on Infor-
mation coding Techniques with TMH Publishers. She is currently
pursuing her research at Anna University Tiruchirappalli , India. Her
research interests are in Embedded systems, Multimedia Networks
and Network Processor .
Dr.P. Seethalakshmi has received
her B.E. degree in Electronics and Communication Engineering in
1991 and M.E. degree in Applied Electronics in 1995 from Bhara-
thiar University, India. She obtained her doctoral degree from Anna
University Chennai, India in the year 2004. She has 15 years of
teaching experience. She is Director/ CAE, Anna University Thiruchi-
rappalli. Her areas of research includes Multimedia Streaming, Wire-
less Networks, Network Processors and Web Services.