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Low Power and Area Consumption Custom Networks-On-Chip Architectures Using RST Algorithms

Low Power and Area Consumption Custom Networks-On-Chip Architectures Using RST Algorithms

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Published by ijcsis
Abstract: Network-on-Chip (NoC) architectures with optimized topologies have been shown to be superior to regular architectures (such as mesh) for application specific multiprocessor System-on-Chip (MPSoC) devices. The application specific NoC design problem takes, as input the system-level floorplan of the computation architecture .The objective is to generate an area and power optimized NoC topology. In this work, we consider the problem of synthesizing custom networks-on-chip (NoC) architectures that are optimized. Both the physical links and routers determine the power consumption of the NoC architecture. Our problem formulation is based on the decomposition of the problem into the inter-related steps of finding good flow partitions, and providing an optimized network implementation for the derived topologies. We used Rectilinear–Steiner-Tree (RST)-based algorithms for generating efficient and optimized network topologies. Experimental results on a variety of NoC benchmarks showed that our synthesis results were achieve reduction in power consumption and average hop count over different mesh implementations. We analyze the quality of the results and solution times of the proposed techniques by extensive experimentation with realistic benchmarks and comparisons with regular mesh-based NoC architectures.

Index Terms—Multicast routing, network-onchip (NoC), synthesis, system-on-chip (SoC), topology.
Abstract: Network-on-Chip (NoC) architectures with optimized topologies have been shown to be superior to regular architectures (such as mesh) for application specific multiprocessor System-on-Chip (MPSoC) devices. The application specific NoC design problem takes, as input the system-level floorplan of the computation architecture .The objective is to generate an area and power optimized NoC topology. In this work, we consider the problem of synthesizing custom networks-on-chip (NoC) architectures that are optimized. Both the physical links and routers determine the power consumption of the NoC architecture. Our problem formulation is based on the decomposition of the problem into the inter-related steps of finding good flow partitions, and providing an optimized network implementation for the derived topologies. We used Rectilinear–Steiner-Tree (RST)-based algorithms for generating efficient and optimized network topologies. Experimental results on a variety of NoC benchmarks showed that our synthesis results were achieve reduction in power consumption and average hop count over different mesh implementations. We analyze the quality of the results and solution times of the proposed techniques by extensive experimentation with realistic benchmarks and comparisons with regular mesh-based NoC architectures.

Index Terms—Multicast routing, network-onchip (NoC), synthesis, system-on-chip (SoC), topology.

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Published by: ijcsis on Oct 10, 2010
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Low Power and Area Consumption Custom Networks-On-ChipArchitectures Using RST Algorithms
1
P.Ezhumali
2
Dr.C.Arun
1
Professor, Dept of Computer Science Engineering
2
Asst. Professor, Dept of Electronics and CommunicationRalalakshmi Engineering College, Thandalam-602 105, Chennai, India
1
carunece@gmail.com,2ezhu.pubs@gmail.com 
Abstract
:
 
Network-on-Chip (NoC)architectures with optimized topologies havebeen shown to be superior to regulararchitectures (such as mesh) for applicationspecific multiprocessor System-on-Chip(MPSoC) devices. The application specific NoCdesign problem takes, as input the system-levelfloorplan of the computation architecture .Theobjective is to generate an area and poweroptimized NoC topology. In this work, weconsider the problem of synthesizing customnetworks-on-chip (NoC) architectures that areoptimized. Both the physical links and routersdetermine the power consumption of the NoCarchitecture. Our problem formulation is basedon the decomposition of the problem into theinter-related steps of finding good flowpartitions, and providing an optimized network implementation for the derived topologies. Weused Rectilinear–Steiner-Tree (RST)-basedalgorithms for generating efficient andoptimized network topologies. Experimentalresults on a variety of NoC benchmarks showedthat our synthesis results were achieve reductionin power consumption and average hop countover different mesh implementations. Weanalyze the quality of the results and solutiontimes of the proposed techniques by extensiveexperimentation with realistic benchmarks andcomparisons with regular mesh-based NoCarchitectures.
 Index Terms—
Multicast routing, network-on-chip (NoC), synthesis, system-on-chip (SoC),topology
.1.Introduction
Network-on-Chip (NoC) is an emergingparadigm for communications within largeVLSI systems implemented on a single siliconchip. The layered-stack approach to the designof the on-chip intercore communications is theNetwork-on-Chip (NOC) methodology. In aNoC system, modules such as processor cores,memories and specialized IP blocks exchangedata using a network as a "publictransportation" sub-system for the informationtraffic. A NoC is constructed from multiplepoint-to-point data links interconnected byswitches (a.k.a. routers), such that messagescan be relayed from any source module to anydestination module over several links, bymaking routing decisions at the switches.A NoC is similar to a moderntelecommunications network, using digital bit-packet switching over multiplexed links.Although packet switching is sometimesclaimed as necessity for a NoC, there are severalNoC proposals utilizing circuit-switchingtechniques. This definition based on routers isusually interpreted so that a single shared bus, asingle crossbar switch or a point-to-pointnetwork is not NoCs but practically all othertopologies are. This is somewhat confusingsince all above-mentioned are networks (theyenable communication between two or moredevices) but they are not considered as network-on-chips. Note that some erroneously use NoCas a synonym for mesh topology although NoCparadigm does not dictate the topology.Likewise, the regularity of topology issometimes considered as a requirement, whichis, obviously, not the case in researchconcentrating on "application-specific NoCtopology synthesis".
(IJCSIS) International Journal of Computer Science and Information Security,Vol. 8, No. 6, September 2010107http://sites.google.com/site/ijcsis/ISSN 1947-5500
 
 figure.1 Topological illustration of a4-by-4 grid structured NoC.The wires in the links of the NoC are sharedby many signals. A high level of parallelismis achieved, because all links in the NoC canoperate simultaneously on different datapackets. Therefore, as the complexity of integrated systems keeps growing, a NoCprovides enhanced performance (such asthroughput) and scalability in comparisonwith previous communication architectures(e.g., dedicated point-to-point signal wires,shared buses, or segmented buses withbridges). Of course, the algorithms must bedesigned in such a way that they offer largeparallelism and can hence utilize thepotential of NoC.Traditionally, ICs have been designed withdedicated point-to-point connections, with onewire dedicated to each signal. For largedesigns, in particular, this has severallimitations from a physical design viewpoint.The wires occupy much of the area of the chip,and in nanometer CMOS technology,interconnects dominate both performance anddynamic power dissipation, as signalpropagation in wires across the chip requiresmultiple clock cycles. NoC links can reducethe complexity of designing wires forpredictable speed, power, noise, reliability,etc., because of their regular, well-controlledstructure. From a system design viewpoint,with the advent of multi-core processorsystems, a network is a natural architecturalchoice. A NoC can provide separation betweencomputation and communication; supportmodularity and IP reuse via standardinterfaces, handle synchronization issues,serve as a platform for system test, and, hence,increase engineering productivity.Although NoCs can borrow concepts andtechniques from the well-established domainof computer networking, it is impractical toblindly reuse features of "classical" computernetworks and symmetric multiprocessors. Inparticular, NoC switches should be small,energy-efficient, and fast. Neglecting theseaspects along with proper, quantitativecomparison was typical for early NoCresearch but nowadays they are considered inmore detail. The routing algorithms shouldbe implemented by simple logic, and thenumber of data buffers should be minimal.Network topology and properties may beapplication-specific. Research on NoC is nowexpanding very rapidly, and there are severalcompanies and universities that are involved.Figure 1 shows how a NoC, in comparisonwith shared buses, could be occupied withvarious components as resources
2.EXISTING RELATED WORKS
So far, the communication problems facedby System on chip were tackled by making useof regular Network on chip architectures. Thefollowing are the list of popular regular NoCarchitectures:Mesh Architecture.Torus Architecture.Butterfly Fat Tree Architecture.
(IJCSIS) International Journal of Computer Science and Information Security,Vol. 8, No. 6, September 2010108http://sites.google.com/site/ijcsis/ISSN 1947-5500
 
Extended Butterfly Fat Tree ArchitectureThe NoC design problem has receivedconsiderable attention in the literature. Towlesand Dally [1] and Benini and De Micheli [2]motivated the NoC paradigm. Several existingNoC solutions have addressed the mappingproblem to a regular mesh-based NoCarchitecture [3], [4]. Hu and Marculescu [3]proposed a branch-and-bound algorithm forthe mapping of computation cores on to mesh-based NoC architectures. Murali
et al.
[4]described a fast algorithm for mesh-based NoCarchitectures that considers different routingfunctions, delay constraints, and bandwidthrequirements. On the problem of designingcustom NoC architectures without assumingexisting network architecture, a number of techniques have been proposed [5]–[10]. Pinto
et al.
[7] presented techniques for theconstraint-driven communication architecturesynthesis of point-to-point links by usingheuristic-based -way merging. Their techniqueis limited to topologies with specific structuresthat have only two routers between eachsource and sink pair. Ogras
et al.
[5], [6]proposed graph decomposition and long link insertion techniques for application-specificNoC architectures. Srinivasan
et al.
[8], [9]presented NoC synthesis algorithms thatconsider system-level floor planning, but theirsolutions only considered solutions based on aslicing floorplan where router locations arerestricted to corners of cores and links runaround cores. Murali
et al.
[10] presented aninnovative deadlock-free NoC synthesis flowwith detailed backend integration that alsoconsiders the floorplanning process. Theproposed approach is based on the min-cutpartitioning of cores to routers. This work presents a synthesis approach based on a setpartitioning formulation that considersmulticast traffic, Although different intopology and some other aspects, all the abovepapers essentially advocate the advantages of using NoCs and regularity as effective meansto design high performance SoCs. While thesepapers mostly focus on the concept of regularNoC architecture (discussing the overalladvantages and challenges), to the best of ourknowledge, our work is better than previouscustom NoC synthesis formulations andefficient way to solve it.
PROPOSED SYSTEM3.1 PROBLEM DEFINITION
 
We consider the problem of synthesizingcustom networks-on-chip (NoC)architectures that are optimized for agiven application.
 
We divide the problem statement intothe flowing interrelated steps:Physical topology Construction.Power and Area Comparisons
3.2 SYSTEM ARCHITECTURE
 Figure. 2 Proposed System ArchitectureOur NoC synthesis design flow is depicted inFigure 2. The major elements in the designflow are elaborated as follows.
Input Specification
:
The input specificationto our design flow consists of a list of modules. As observed in recent trends, manymodern SoC designs combine both hard andsoft modules as well as both packet-basednetwork communications and conventional
(IJCSIS) International Journal of Computer Science and Information Security,Vol. 8, No. 6, September 2010109http://sites.google.com/site/ijcsis/ISSN 1947-5500

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/*********** DO NOT ALTER ANYTHING BELOW THIS LINE ! ************/ var s_code=s.t();if(s_code)document.write(s_code)//-->