Extended Butterfly Fat Tree ArchitectureThe NoC design problem has receivedconsiderable attention in the literature. Towlesand Dally  and Benini and De Micheli motivated the NoC paradigm. Several existingNoC solutions have addressed the mappingproblem to a regular mesh-based NoCarchitecture , . Hu and Marculescu proposed a branch-and-bound algorithm forthe mapping of computation cores on to mesh-based NoC architectures. Murali
described a fast algorithm for mesh-based NoCarchitectures that considers different routingfunctions, delay constraints, and bandwidthrequirements. On the problem of designingcustom NoC architectures without assumingexisting network architecture, a number of techniques have been proposed –. Pinto
 presented techniques for theconstraint-driven communication architecturesynthesis of point-to-point links by usingheuristic-based -way merging. Their techniqueis limited to topologies with specific structuresthat have only two routers between eachsource and sink pair. Ogras
, proposed graph decomposition and long link insertion techniques for application-specificNoC architectures. Srinivasan
, presented NoC synthesis algorithms thatconsider system-level floor planning, but theirsolutions only considered solutions based on aslicing floorplan where router locations arerestricted to corners of cores and links runaround cores. Murali
 presented aninnovative deadlock-free NoC synthesis flowwith detailed backend integration that alsoconsiders the floorplanning process. Theproposed approach is based on the min-cutpartitioning of cores to routers. This work presents a synthesis approach based on a setpartitioning formulation that considersmulticast traffic, Although different intopology and some other aspects, all the abovepapers essentially advocate the advantages of using NoCs and regularity as effective meansto design high performance SoCs. While thesepapers mostly focus on the concept of regularNoC architecture (discussing the overalladvantages and challenges), to the best of ourknowledge, our work is better than previouscustom NoC synthesis formulations andefficient way to solve it.
PROPOSED SYSTEM3.1 PROBLEM DEFINITION
We consider the problem of synthesizingcustom networks-on-chip (NoC)architectures that are optimized for agiven application.
We divide the problem statement intothe flowing interrelated steps:Physical topology Construction.Power and Area Comparisons
3.2 SYSTEM ARCHITECTURE
Figure. 2 Proposed System ArchitectureOur NoC synthesis design flow is depicted inFigure 2. The major elements in the designflow are elaborated as follows.
The input specificationto our design flow consists of a list of modules. As observed in recent trends, manymodern SoC designs combine both hard andsoft modules as well as both packet-basednetwork communications and conventional
(IJCSIS) International Journal of Computer Science and Information Security,Vol. 8, No. 6, September 2010109http://sites.google.com/site/ijcsis/ISSN 1947-5500