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tda7330

tda7330

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Published by wih
RDS Chip
RDS Chip

More info:

Categories:Types, Brochures
Published by: wih on Apr 27, 2007
Copyright:Attribution Non-commercial

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01/01/2013

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TDA7330B
SINGLE CHIP RDS DEMODULATOR + FILTER
ADVANCE DATA
HIGH PERFORMANCE, 57KHz BANDPASSFILTER(8th ORDER)FILTER ADJUSTMENT FREE AND WITHOUTEXTERNAL COMPONENTSPURELY DIGITAL RDS DEMODULATIONWITHOUTEXTERNAL COMPONENTSARI (SK INDICATION) AND RDS SIGNALQUALITYOUTPUT4.332MHzCRYSTALOSCILLATOR(8.664MHzOPTIONAL)LOW NOISE MIXED BIPOLAR/CMOS TECH-NOLOGY
DESCRIPTION
The TDA7330B is a RDS demodulator. It recov-ers the additional inaudible RDS informationwhich is transmitted by FM radio broadcastingstations.The output data signal (RDDA) and clock signal(RDCL) can be further processed by a suitableRDSdecoder(microprocessor).The device operates in accordance with the EBU(EuropeanBroadcastingUnion) specifications.The IC includes a 2nd order antialiasing input fil-ter, a 57KHz switched capacitor band pass filter,a smoothing filter and cross detector, a bit rateclock recovery circuit, a 57KHz PLL, BI-PHASEPSK decoder, differentialdecoding circuit, ARI in-dicationand RDSsignal qualityoutput.
Thisisadvancedinformationonanewproductnowin developmentorundergoingevaluation.Detailsaresubjectto changewithoutnotice.notice.
April1993
BLOCKDIAGRAM
DIP20 SO20ORDERING NUMBERS:
TDA7330B TDA7330BD1/9
 
ABSOLUTEMAXIMUMRATINGS
Symbol Parameter Value Unit
V
CC
Supply Voltage 7 VT
op
Operating Temperature Range -40 to 85
°
CT
stg
Storage Temperature -40 to 150
°
C
THERMAL DATA
Symbol Description DIP20 SO20 Unit
R
th j-case
Thermal Resistance Junction-case Typ. 100 200
°
C/W
PINCONNECTION
(Top view)
Nr. Name Description
1234567891011121314151617181920MUXINV
ref
COMPFIL OUTGNDT1T3T4OSC OUTOSC INT57RDCLRDDAQUALARIV
CC
T2FSELTMPORRDS input signal.Reference voltageNot inverting comparatorinput (smoothing filter)Filter OutputGroundTesting output pin (not to be used)Testing output pin (not to be used)Testing output pin (not to be used)Oscillator outputOscillator InputTesting output pin: 57KHz clock outputRDS clock output (1187.5Hz)RDS data outputOutput forsignal qualityindication (High= good)Output forARI indication(High when RDS + ARI signals are present)(High when only ARI is present)(Low when only RDS is present)(indefinedwhen no signal is present)Supply VoltageTesting output pin (not to be used)Frequency selector pin: open = 4.332MHz, closed to V
CC
= 8.664MHzTest mode pin (open = normal RUN)(closed toV
CC
= Test mode)Reset Input for testing (active high)
PINFUNCTION
TDA7330B
2/9
 
ELECTRICALCHARACTERISTICS
(V
CC
= 5V,Tamb = 25
°
C; R
g
=600
; fosc= 4.332MHz;V
IN
=20mVrms unlessotherwisespecified)
Symbol Parameter TestCondition Min. Typ. Max. Unit
SUPPLY
V
CC
Supply Voltage 4.5 5 5.5 VI
S
Supply Current 9 mAR
POR
POR PullDown Resistor pin 20 40 K
POR
ON
POR Threshold 2.5 V
FILTER(measuredan pin 4 FILOUT)
F
C
Center Frequency 56.5 57 57.5 KHzBW 3dB Bandwidth 2.5 3 3.5 KHzG Gain f = 57KHz 18 20 22 dBA Attenuation
f = +4KHzf = 38KHz; V
i
= 500mVrmsf = 67KHz; V
i
= 250mVrms185035228050dBdBdB
Ph Phase non linearity A (seenote1)B (seenote1)C (see note1)0.51257.510DEGDEGDEGR
i
Input Impedance 100 160 200 K
S/N Signal to Noise Ratio V
i
= 3mVrms 30 40 dBV
i
Maximum InputSignal Capability f =19KHz; T3< –40dB (see note2)f = 57KHz (RDS + ARI)150VrmsmVrmsR
L
Load Impedance Pin 4 100 K
CROSS DETECTOR
RA Resistance pin 3-4 15 21 28 K
OSCILLATOR
F
OSC
Oscillator Frequency F
SEL
= Open (*)F
SEL
= Closed to V
CC
(**)4.3328.664MHzMHzVCLL Clock Input levelLOW (pin10) 1 VVCLH Clock Input Level HIGH (pin 10) 4 VOutput Amplitude (pin 9) 4.5 V
PP
(*) FSEL pin hasan internal 40K
pulldown resistor A 4.332MHz QUARTZ mustbe used (**)A 8.664MHz QUARTZ must be used.
DEMODULATOR
f
O
Max Oscillator Deviation F
SEL
= Open + 1.2 KHzS
RDS
RDS Detection Sensitivity 1 mVrmsS
ARI
ARI DetectionSensitivity 3 mVrmsT
lock
RDS Lockup Time 100 msV
OH
Output HIGH Voltage I
L
= 0.5mA; pins 12, 13, 14, 15 4 VV
OL
Output LOW Voltage I
L
= 0.5mA; pins12, 13, 14, 15 1 Vf
RDS
Data Rate for RDS RDCL pin 1187.5 Hzt
D
RDDA Transitionversus RDCL (see figure 2) 4.3
µ
sec
Note(1):
The phasenon linearity isdefined as:
Ph = | -2
φ
f2 +
φ
f1 +
φ
f3 |where
φ
fxis theinput-output phasedifference at the frequency fx (x= 1,2,3)
TDA7330B
3/9

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