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This project makes use of the Spartan-3E FPGA Starter Kit Board Expansion Connectors,
specifically the 6-Pin Accessory Headers, Header J1 and Header J2. Using the expansion
connector of the Spartan-3E, we will input data from a keypad. The key pressed in the keypad
will be displayed in the first line of the on-board Liquid Crystal Display (LCD) of the Spartan-3E.
A numeric keypad to a MM74C922 will be used to output a five-bit data to the 6-pin headers.
The four-bit data will be connected to the J1 header and the data available which is the fifth bit
will be connected to the J2 header. The bit in the J2 header is a check bit if there is a key
pressed. The data sent in the J1 header are the data to be displayed in the LCD. The LCD is
configured to display the desired number to be displayed or the key pressed in the keypad.
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Over-all Block Diagram
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Entity Diagram(s)
For keypad_input.vhd:
For lcd_expansion.vhd:
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For top_module.vhd:
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Source Code(s)
--keypad_module.vhd:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity keypad_module is
Port ( keypress_in : in STD_LOGIC_VECTOR (4 downto 0);
keypress_out : out STD_LOGIC_VECTOR (11 downto 0));
end keypad_module;
begin
process(keypress_in)
begin
case keypress_in is
when "10000" => temp2 := "100011100001"; -- 0 1
when "10001" => temp2 := "100011100010"; -- 1 2
when "10010" => temp2 := "100011100011"; -- 2 3
when "10100" => temp2 := "100011100100"; -- 4 4
when "10101" => temp2 := "100011100101"; -- 5 5
when "10110" => temp2 := "100011100110"; -- 6 6
when "11000" => temp2 := "100011100111"; -- 8 7
when "11001" => temp2 := "100011101000"; -- 9 8
when "11010" => temp2 := "100011101001"; -- 10 9
when "11100" => temp2 := "100010101010"; -- 12 *
when "11101" => temp2 := "100011100000"; -- 13 0
when "11110" => temp2 := "100010100011"; -- 14 C
when others => null;
end case;
end process;
end Behavioral;
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--lcd_module.vhd:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lcd_module is
Port ( clk: in STD_LOGIC;
sf_ce0, rs, rw, en : out STD_LOGIC;
lcd_data : out STD_LOGIC_VECTOR (3 DOWNTO 0);
keypad_output : in STD_LOGIC_VECTOR (11 downto 0));
end lcd_module;
begin
process (clk)
begin
if rising_edge(clk) then
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------------- Data operation for LCD ----------------------------------
end case;
end if;
end process;
en <= final_out(6);
rs <= final_out(5);
rw <= final_out(4);
lcd_data<= final_out(3 downto 0);
end Behavioral;
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--top_module.vhd:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity top_module is
Port ( data_in : in STD_LOGIC_VECTOR (4 downto 0);
clk : in STD_LOGIC;
sf_ce0, rs, rw, en : out STD_LOGIC;
data_out: out STD_LOGIC_VECTOR (3 downto 0));
end top_module;
component keypad_module is
Port ( keypress_in : in STD_LOGIC_VECTOR (4 downto 0);
keypress_out : out STD_LOGIC_VECTOR (11 downto 0));
end component;
component lcd_module is
Port ( clk: in STD_LOGIC;
sf_ce0, rs, rw, en : out STD_LOGIC;
lcd_data : out STD_LOGIC_VECTOR (3 DOWNTO 0);
keypad_output : in STD_LOGIC_VECTOR (11 downto 0));
end component;
begin
end structural;
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Simulation Waveform
UCF File(s)
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