Resistor Area

1.2 RW R (WR  S R )
AR 
Rs

Where R is the desired resistance

Rs is the applicable sheet resistance
WR is the width of the resistor and SR is the spacing
between adjacent resistor stripes.

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 Capacitor Area

C
Acap 
C unit  area

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 MOS Transistor

AMOS  1.3W g ( L g  S gg )

Wg is the width of the gate, Lg is the length of the gate.

Sgg is the space between adjacent gate stripes of a multi-
finger transistor.
If transistor need guard rings or separate well, its area
will be larger than this estimation.

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 MOS Power Transistor
Rsp
APWRMOS 
Rds ( on )  RP

RP: package resistance (including bondwire and leadframe)

Rds(on): on resistance of the MOS power transistor
Rsp:measured specific on-resistance

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 Cell Area

Acell  Pf  A

Pf is the packing factor and is about 1.5 to 2.0 for

CMOS technology.

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 Core Area

Acore  R f Pf  Acell  Pf  A pwr

Rf is the routing factor, which accounts for the area

consumed by top-level wiring, in the range of 1.0 to 1.5..

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 Die Area

Adie  ( Acore  2W padring  Wscribe ) 2

Scribe width Wscribe: typically 75 to 125 m.

Padring width: typically 130% of the bondpad

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 Die Area Factors
Three factors:
Circuitry it contains (CORE)
Pads around its periphery (PADRING)
Scribe streets separating it from adjacent dice.

Core limited or Pad limited ?

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 Die Perimeter
The minimum die perimeter Pmin required to place the pads:

Pmin  ( N pad  4)(W pad  S pad )  4Wscribe  8L corner

Spad is the minimum spacing allowed between adjacent

pads.
Lcorner minimum allowed distance from the die corner to
the nearest bondpads.

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 Perimeter Utilization Factor
Pmin
P
4 Adie
P<1: core-limited;
P>1: pad-limited. The the total die area with a square
aspect ratio:
2 2
 Pmin  Pmin
Adie   
 4  16
Fuding Ge: Die Area Es 10
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