CONFIDENTIAL CS/APR 2006/ITT430

UNIVERSITI TEKNOLOGI MARA

FINAL EXAMINATION

COURSE MICROPROCESSOR
COURSE CODE ITT430

EXAMINATION APRIL 2006

TIME 3 HOURS

INSTRUCTIONS TO CANDIDATES

1. This question paper consists of three (3) parts : PART A (25 Questions)
PART B (25 Questions)
PART C (6 Questions)

2. Answer ALL questions from all three (3) parts.

i) Answer PART A in the Objective Answer Sheet.

ii) Answer PART B in the True/False Answer Sheet.
iii) Answer PART C in the Answer Booklet. Start each answer on a new page.

3. Do not bring any material into the examination room unless permission is given by the
invigilator.

4. Please check to make sure that this examination pack consists of:

i) the Question Paper

ii) an Answer Booklet - provided by the Faculty
iii) a True/False Answer Sheet - provided by the Faculty
iv) an Objective Answer Sheet - provided by the Faculty

DO NOT TURN THIS PAGE UNTIL YOU ARE TOLD TO DO SO

This examination paper consists of 14 printed pages
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CONFIDENTIAL 2 CS/APR 2006/ITT430

PART A (25 marks)

For each of the following questions, choose ONE suitable answer and mark the answer on
the Objective Answer Sheet provided.

1. Nine bits of the status register indicate conditions that are produced as the result of
executing an instruction. How many of them represent control flags ?

A. 3
B. 4
C. 5
D. 6

2. The condition tested for the following jump instructions are similar EXCEPT

A. JAE
B. JB
C. JC
D. JNE

3. Which of the following timing properties defined for the read cycle of an EPROM ?

I Access time (tACC)

II Chip-enable time (ICE)
III Chip-deselect time (tDF)

A. I
B. I, II
C. II, III
D. I, II, III

What is the content of AH register to invoke the interrupt 16H so that it detects a key
press ?

A. (AH)=01H
B. (AH)=02H
C. (AH)=09H
D. (AH)=OAH

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5. In a sixty-four-line parallel output circuit for an 8088-based microcomputer, if the

address put on the bus during an output bus cycle is 800A16, which output port the
data will be written to ?

A. port 0
B. port 2
C. port 4
D. none of the above

6. Which flags are tested by the various conditional loop instructions ?

A. CF
B. SF
C. OF
D. ZF

7. What are the key differences between NMI and the other external hardware initiated
interrupts ?

I NMI is masked out by IF

II NMI is initiated from the NMI input lead instead of from the INTR input.
III NMI input is edge-triggered instead of level sensitive.

A. I, II
B. I, III
C. II, III
D. I, (Mil

8. Which of the following status flags will be shown after executing the following
instructions in the DEBUG trace ?

MOVAL, C
CMP AL, -1
CMP AL, -C

A. NV UP El PL NZ NA PO CY
B. NV UP Dl NG NZ NA PO NC
C. NV UP El PL ZR NA PE NC
D. NV UP El PL NZ NA PE CY

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9. How many bytes are required to encode the instruction "MOV Dl, 1234H" ?

A. 2 bytes
B. 3 bytes
C. 4 bytes
D. 5 bytes

10. The following statements are all true EXCEPT

A. If an external device wants to take control of the system bus, it signals this
fact to the MPU by switching HOLD to logic 1.
B. In the hold state, signal lines AD0 through AD7 will be switched to logic 1.
C. Other signal lines such as SSO, IO/M, DT/R, DEN and INTR are all put into
high-Z state during the hold state.
D. The 8088 signals external devices that the signal lines are in the high-Z
state by switch its HLDA output to logic 1.

11. What happens to the CF and ZF status flags as the following sequence of
instructions is executed ? Assume that they are both initially cleared.

MOV AL, AAH

AND AL, 55H
CMP AL, 00

A. (CF)=0, (ZF)=0
B. (CF)=0, (ZF)=1
C. (CF)=1,(ZF)=0
D. (CF)=1,(ZF)=1

12. What is the value of BX after executing the following instructions ?

MOV BX, FOFOH

MOV CL, 4
CLC
RCR BX, CL

A. (BX)=OFOFH
B. (BX)=OFFOH
C. (BX)=FOFOH
D. (BX)=FFOOH

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13. What is the content of the AL register after executing the following instructions ?

MOVAL, CAM
ANDAL, OFH
OR AL, ADH
XORAL, OFH
NOTAL

A. 5FH
B. F5H
C. FAH
D. AFH

14. What value must be written to the control register of the 82C55A to configure the
device such that port A and port B are configured as output ports and port C is set up
as input port in mode 0 operation ?

A. 88H
B. 89H
C. C8H
D. C9H

15. The following statements are all true EXCEPT

A. The maximum-mode configuration is mainly used for implementing a

multiprocessor/coprocessor system environment.
B. In the maximum-mode, 8088/8086 outputs a status code on three signal line
S0, ST and S2 prior to the initialization of each bus cycle.
C. The 3-bit bus status code identifies which type of bus cycle is to follow and
are input to the external bus controller device, 8288.
D. The 8088 produces one command signals for each bus cycle.

16. State the value of the flag register after executing the following instructions.

MOVDX, F11FH
XORDX, 1AA1H
ANDDX, 1111H

A. CF=0, PF=0, OF=0, ZF=0 and SF=0

B. CF=0, PF=1, OF=0 ZF=1 and SF=0
C. CF=1, PF=0, OF=0, ZF=0 and SF=0
D. CF=1, PF=1, OF=0, ZF=0 and SF=0

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17. What is the content of AX after executing the following sequence of instructions ?

MOV AX,-1
MOV BL, 3
IDIV BL
MOV AX,-11
SAR AX, 1

A. (AX)=FFF7H
B. (AX)=FFF9H
C. (AX)=FFFBH
D. (AX)=FFFDH

18. Specify the mode byte for DMA channel 3 if it is to transfer data from an input
peripheral device to a memory buffer starting at address A00016 and ending at
AFFF16. Ensure that the microprocessor is not completely locked off the bus during
the DMA cycle. Moreover, at the end of each DMA cycle, the channel is to be
reinitialized so that the same buffer is filled when the next DMA operation is initiated.

A. 5616
B. 5716
C. 8616
D. 8716

19. Which parallel I/O port in memory-mapped 82C55A of the 8088-based

microcomputer is selected for operation when the memory address output on the bus
is 00412ie?

A. port B on PPI 0
B. port B on PPI 2
C. port B on PPI 4
D. port B on PPI 6

20. When the instruction POP AX is executed, what address bus status code and
memory bus cycle code are output by the 8088 in a maximum mode microcomputer
system ?

A. S4S3=01 and S2S1S0=101

B. S4S3=01 andS2S1S0=110
C. S4S3=10 and 828^0=101
D. 8483=10 and S2S1S0=110

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21. In an 8086-based microcomputer system, what are the logic levels of A0 and BHE
when the instruction PUSH AX is executed ?

A. A0=0 and BHE=0

B. A0=0 and BHE=1
C. Ao=1 and BHE=0
D. A0=1 and BHE=1

22. The following control signals are provided to support the memory and I/O interfaces
of the 8088/8086 during the minimum mode EXCEPT

A. ALE
B. READY
C. LOCK
D. BHE

23. In the maximum-mode I/O interface of 8088 system, what are the logic levels of
IORC, IOWC, and AIOWC during an output bus cycle ?

A. IORC= 1, IOWC=0, and AIOWC=0

B. IORC= 1, IOWC=0, and AIOWC=0
C. IORC= 0, IOWC=1, and AIOWC=1
D. IORC= 0, IOWC=1, and AIOWC=1

24. What would be the address of the vector 60, CS6o and IP6o be stored in memory ?

A. CS60=F2H and IP60=FOH

B. CS60=FOH and IP60=F2H
C. CS60=80H and IP60=F2H
D. CS60=82H and IP60=80H

25. When an application program is tested on an 80486SX-based microcomputer

system, it is found that 1,340 instructions and data accesses are from the internal
cache memory and 97 are from main memory. What is the hit rate ?

A. 93.2 %
B. 95.5 %
C. 96.8 %
D. 98.6 %

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PARTB (25 marks)

For each of the following questions, answer either TRUE or FALSE and mark your answer
on the TRUE/FALSE Answer Sheet provided.

1. T F The generation of the physical address involves combining a 16-bit

offset value that is located in the instruction pointer, a base pointer, an
index register, OR a pointer register AND a 16-bit segment base value
that is located in one of the segment register.

2. T F The dedicated memory (OOOOOH - 00013H) are used for the storage of
the pointers to 8088's internal interrupt service routines and user-defined
interrupts.

3. T F If the ASCII representation for character "A" is 41H then the ASCII
representation for character "Q" is 51 H.

4. T F The jump will happen when executing the following instructions.

MOV CL, 5
SUB AL, AL
SHLAL, CL
JNC TARGET

5. T F The highest address word of a pointer represents the segment base

address while the lower address word represents the offset.

6. T F The "JNZ DLY" instruction will get executed 1020 times if the following
delay loop is executed.

MOV CX, 03FAH

DLY: DEC CX
NOP
JNZ DLY
NXT: .....................

7. T F If (AL)=FAH, the new contents of AX are FFFAH after executing the

instruction "CBW".

8. T F The values of Q.ST and QS2 produced in minimum mode when the queue
status is empty are 0 and 0 respectively.

9. T F The stack pointer is used to access data within the stack segment of
memory and commonly used to reference subroutine parameters.

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10. T F 875 ns is the duration of the bus cycle in the 8088-based microcomputer
if the clock is 8 MHz and the three wait states are inserted.

11. T F If (SP)=20A9H, the offset address of the first location of the stack that is
available to pop data is 20ABH.

12. T F All conditional jumps are short jumps where the address of the target
must be within -127 to 128 bytes of the IP.

13. T F The two bits S2 and ST of the status signal are used to form a binary
code that identifies which of the internal segment registers is used to
generate the physical address.

14. T F Two bus cycles are required to read a word at memory address 0123316
of an 8086-based microcomputer.

15. T F All Pentium processors have two execution units (pipelines) capable of
executing two instructions with one clock.

16. T F The IO/M, DT/R and SSO control signals indicate the type of bus cycle
in progress and the direction data are to be transferred over the bus.

17. T F Status bits S3 through S6 are output on the upper four address bus lines
A16 through A19 at the beginning of T2.

18. T F If the contents of registers AX and BL are -21 and 2 respectively, then
the content of AL is FOH after executing the instruction "IDIV BL".

19. T F Word-wide I/O ports are aligned at even address boundaries.

20. T F The protected-mode address pointer table is called interrupt descriptor

table.

21. T F The 386 addresses 4 Gbytes, the 286 addresses 32 Mbytes, and the
8088/8086 addresses 1 Mbyte.

22. T F The following instructions will output the data FF16 to a byte-wide output
port at address AB16 of the I/O address space.

MOV AH, FFH

OUT ABH, AH

23. T F Netburst microarchitecture is used to design the Pentium IV processor.

24. T F Data parity and address parity are the only two kinds of parity which are
supported on the Pentium processor's bus interface.

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25. T F All 386SX, 386DX, 486SX and 486DX microprocessors have 32 bits
address bus and 32 bits data bus.

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CONFIDENTIAL 11 CS/APR 2006/ITT430

PART C (50 marks)

Answer ALL questions.

QUESTION 1

Encode the following instructions using the information given in Table 1 and Table 2.
Assume that the opcode for the MOV, PUSH and ADD operations are 100011, 01010 and
000000 respectively.

a) MOV [BP][DI] + 6789H, DS

b) PUSH AX
c) ADD BX, ABCDH + [BX][SI]

Tablel

REG w=o W=l

000 AL AX
001 CL CX
010 DL DX
on BL BX
100 AH SP
101 CH BP
110 DH SI
111 BH DI

Table 2

MOD=11 EFFECTIVE ADDRESS CALCULATION

R/M w=o W=l R/M MOD=00 MOD=01 MOD=10
000 AL AX 000 (BX)+(SI) (BX)+(SI)+D8 (BX)+(SI)+D16
001 CL CX 001 (BX)+(DI) (BX)+(DI)+D8 (BX)+(DI)+D16
010 DL DX 010 (BP)+(SI) (BP)+(SI)+D8 (BP)+(SI)+D16
on BL BX on (BP)+(DI) (BP)+(DI)+D8 (BP)+(DI)+D16
100 AH SP 100 (SI) (SI)+D8 (SI)+D16
101 CH BP 101 (DI) (DI)+D8 (DI)+D16
110 DH SI 110 Dir. address (BP)+D8 (BP)+D16
111 BH DI 111 (BX) (BX)+D8 (BX)+D16

(6 marks)

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CONFIDENTIAL 12 CS/APR 2006/ITT430

QUESTION 2

a) Describe the differences between memory mapped I/O and isolated I/O.
(4 marks)

b) Explain how to expand the word length of an EPROM using two EPROMs of size 32K
x8.
(3 marks)

c) Explain how to expand the word capacity of EPROM using two EPROMs of size 32K
x8
(3 marks)

QUESTION 3

a) What is the instruction needed to be appended so that a counter counts up from 0 to

99 in BCD ?

SUB AL, AL
ADD AL, 1

(3 marks)

b) Fix the error for the following program which is meant to set the cursor at position
row=14 and column=20.

MOV AH, 02
MOV BH, 00
MOV DH, 14H
MOV DL, 20H
INT 10H

(4 marks)

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CONFIDENTIAL 13 CS/APR 2006/ITT430

QUESTION 4

^ *"

j£ Ju_ h
tteropr»»8»
interface 82 m
BTTfS CJiTS

On** U
RESET BP*tCT « —— / —— »-
fes!J2SJ
f
A|

Aa —— "O
Dnjft j*
^ —— / —— ^

From
ihe
AM ———— 5s
processor ^ t

adttess
bus V ~-\
__>

IQ^P ________

Figure 1 (Addressing an 82C55A PPI)

a) The 82C55A Programmable Peripheral Interface is an LSI peripheral. Explain the

function of this device

(3 marks)

b) The circuit in Figure 1 is an example of how the 82C55A can be interfaced to a

microprocessor. Describe how port A, port B, port C, and control register can be
accessed.

(6 marks)

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CONFIDENTIAL 14 CS/APR 2006/ITT430

QUESTION 5

a) Draw a complete block diagram for a minimum-mode 8088-based microcomputer for

which a 74F138 decoder is used to generate MEMR and MEMW from RD, WR, and
IO/M signals.

(4 marks)

b) If the inputs to a 74F138 decoder are d=1, G2A=0, G2B=0, and CBA=101, which
output is active ?

(2 marks)

c) How many address lines must be decoded to generate five chips select signals ?

(2 marks)

QUESTION 6

a) Explain the main difference between full segment and simplified segment definition ?

(2 marks)

b) Write a complete program using full segment definition that finds the number of zeros
in a 16-bit word.

(8 marks)

END OF QUESTION PAPER

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