Welcome to Scribd, the world's digital library. Read, publish, and share books and documents. See more ➡
Standard view
Full view
of .
×

1.1 Technology Options
1.3 Multiplication Architectures
1.4 Architectural Choices
1.5 Thesis Structure
2.2.1 Booth 3 with Fully Redundant Partial Products
2.2.2 Booth 3 with Partially Redundant Partial Products
2.2.3 Booth with Bias
2.2.4 Redundant Booth 3
2.2.5 Redundant Booth 4
3.1 Deﬁnitions and Terminology
3.1.1 Positive and Negative Logic
3.2 Design Example - 64 bit CLA adder
3.2.1 Group Logic
3.2.3 Remarks on CLA Example
3.3 Design Example - 64 Bit Modiﬁed Ling Adder
3.3.1 Group Logic
3.3.3 Producing the Final Sum
3.3.4 Remarks on Ling Example
3.4 Multiple Generation for Multipliers
3.4.1 Multiply by 3
3.4.2 Short Multiples for Multipliers
3.4.3 Remarks on Multiple Generation
Implementing Multipliers
4.3 Placement methodology
4.3.1 Partial Product Generator
4.3.2 Placing the CSAs
4.3.3 Tree Folding
4.3.4 Optimizations
4.4 Veriﬁcation and Simulation
Exploring the Design Space
5.1 Technology
5.2 High Performance Multiplier Structure
5.2.1 Criteria in Evaluating Multipliers
5.2.2 Test Conﬁgurations
5.3 Which Algorithm?
5.3.1 Conventional Algorithms
5.3.2 Partially Redundant Booth
5.3.3 Improved Booth 3
5.4 Comparing the Algorithms
5.5 Fabrication
5.5.1 Fabrication Results
5.6 Comparison with Other Implementations
5.7 Improvements
5.8 Delay and Wires
Conclusions
Sign Extension in Booth Multipliers
A.1 Sign Extension for Unsigned Multiplication
Figure A.1: 16 bit Booth 2 multiplication with positive partial products
A.1.1 Reducing the Height
A.2 Signed Multiplication
B.2 What’s a Sticky Bit?
0 of .
Results for:
P. 1
CSL-TR-94-617

# CSL-TR-94-617

Ratings: (0)|Views: 498|Likes:

### Availability:

See More
See less

11/05/2011

pdf

text

original

Pages 4 to 15 are not shown in this preview.
Pages 19 to 39 are not shown in this preview.