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The Evolution Of Chip Multi-Processors And Its Role In High Performance And Parallel Computing

The Evolution Of Chip Multi-Processors And Its Role In High Performance And Parallel Computing

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Published by ijcsis
The importance given for today’s computing environment is the support of a number of threads and functional units so that multiple processes can be done simultaneously. At the same time, the processors must not suffer from high heat liberation due over increase in frequencies to attain high speed of the processors and also they must attain high system performance. These situations led to the emergence and the growth of Chip Multi-Processor (CMP) architecture, which forms the basis for this paper. It gives the contribution towards the role of CMPs in parallel and high performance computing environments and the needs to move towards CMP architectures in the near future.
The importance given for today’s computing environment is the support of a number of threads and functional units so that multiple processes can be done simultaneously. At the same time, the processors must not suffer from high heat liberation due over increase in frequencies to attain high speed of the processors and also they must attain high system performance. These situations led to the emergence and the growth of Chip Multi-Processor (CMP) architecture, which forms the basis for this paper. It gives the contribution towards the role of CMPs in parallel and high performance computing environments and the needs to move towards CMP architectures in the near future.

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Published by: ijcsis on Nov 02, 2010
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10/28/2013

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THE EVOLUTION OF CHIP MULTI-PROCESSORS AND ITS ROLE INHIGH PERFORMANCE AND PARALLEL COMPUTING
A.Neela madheswari,
Research Scholar, Anna University, Coimbatore,India.neela.madheswari@gmail.com
Dr.R.S.D.Wahida banu,
Research Supervisor, Anna University, Coimbatore,India.drwahidabanu@gmail.com
 Abstract -
The importance given for today’scomputing environment is the support of anumber of threads and functional units sothat multiple processes can be donesimultaneously. At the same time, theprocessors must not suffer from high heatliberation due over increase in frequencies toattain high speed of the processors and alsothey must attain high system performance.These situations led to the emergence and thegrowth of Chip Multi-Processor (CMP)architecture, which forms the basis for thispaper. It gives the contribution towards therole of CMPs in parallel and highperformance computing environments andthe needs to move towards CMP architecturesin the near future.
 Keywords- CMPs; High Performancecomputing; Grid Computing; Parallel computing; Simultaneous multithreading.
I. INTRODUCTION
Advances in semiconductor technology enablethe integration of billion transistors on a singlechip. Such exponentially increasing transistocounts makes reliability an important designchallenge since a processor’s soft error rategrows in direct proportion to the number of devices being integrated [7]. The huge amount of transistors, on the other hand, leads to the popularity of multi-core processor or chip multi- processor architectures for improved systemthroughput [13].Multi-core processors represents an evolutionarychange in conventional computing as well settingthe new trend for high performance computing(HPC) - but parallelism is nothing new. Intel hasa long history with the concept of parallelismand the development of hardware-enhancedthreading capabilities. Intel has been deliveringthreading capable products for more than adecade. The move towards chip-levelmultiprocessing architectures with a largenumber of cores continues to offer dramaticallyincreased performance and power characteristics[14].In recent years, Chip Multi-Processing (CMP)architectures have been developed to enhance performance and power efficiency through theexploitation of both instruction-level and thread-level parallelism. For instance, the IBMPower5 processor enables two SMT threads to executeon each of its two cores and four chips to beinterconnected to form an eight-core module [8].Intel Montecito, Woodcrest, and AMDAMD64 processors all support dual-cores [9]. Sun alsoshipped eight-core 32-way Niagara processors in2006 [10, 15]. Chip Multi-Processors (CMP)have the advantages of:1. Parallelism of computation: Multiple processors on a chip can execute process threadsconcurrently.2. Processor core density in systems: Highlyscalable enterprise class servers systems as wellas rack-mount servers can be built that fit inseveral processor cores in a small volume.3. Short design cycle and quick time-to-market:Since CMP chips are based on existing processor cores the product schedules can be short [5].
II. MOTIVATION
For the last few years, the software industry hassignificant advances in computing and theemerging grid computing, cloud computing andRich Internet Applications will be the bestexamples for distributed applications. Althoughwe are in machine-based computing now, a shifttowards human-based computing are alsoemerging in which the voice, speech, gesture andcommands of the human can be understand bythe computers and act according to the humansignals. Video conferencing, natural language processing and speech recognition software arecome under this human-based computing asexample. For these kinds of computing, there is aneed for huge computing power with a number 
(IJCSIS) International Journal of Computer Science and Information Security,Vol. 8, No. 7, October 2010111http://sites.google.com/site/ijcsis/ISSN 1947-5500
 
of processors together with the advancement inmulti-processor technologies.In this decade, computer architecture has entereda new ‘multi-core’ era with the advent of ChipMulti-processors (CMP). Many leadingcompanies, Intel, AMD and IBM, havesuccessfully released their multi-core processor series, such as Intel IXP network processors[28], the Cell processor [12], the AMDOpteronTM
 
etc. CMPs have evolved largely dueto the increased power consumption in nanoscaletechnologies which have forced the designers toseek alternative measures instead of devicescaling to improve performance. Increasing parallelism with multiple cores is an effectivestrategy [18].
III. EVOLUTION OF PROCESSOR ARCHITECTURE
Dual and multi-core processor systems are goingto change the dynamics of the market and enablenew innovative designs delivering high performance with an optimized power characteristic. They drive multithreading and parallelism at a higher than instruction level, and provide it to mainstream computing on a massivescale. From an operating system level (OS), theylook like a symmetric multi-processor system(SMP) but they bring lot more advantage thantypical dual or multi- processor systems.Multi-core processing is a long-term strategy for Intel that began more than a decade ago. Intelhas more than 15 multi- core processor projectsunderway and it is on the fast track to deliver multi-core processors in high volume across off of their platform families. Intel’s multi-corearchitecture will possibly feature dozens or evenhundreds of processor cores on a single die. Inaddition to general-purpose cores, Intel multi-core processors will eventually includespecialized cores for processing graphics, speechrecognition algorithms, communication protocols, and more. Many new and significantinnovations designed to optimize the power, performance, and scalability is implemented intothe new multi-core processors [14].According to the number of functional unitsrunning simultaneously, the processor architecture is classified into 3 main typesnamely:
(1)
Single processor architecture, whichdoes not support multiple functionalunits to run simultaneously.
(2)
Simultaneous multithreading (SMT)architecture, which supports multiplethreads to run simultaneously but notthe multiple functional units at any particular time.
(3)
Multi-core architecture or Chip multi- processor (CMP) architecture, whichsupports functional units to runsimultaneous and may support multiplethreads also simultaneously at any particular time.
 A. Single processor architecture
The single processor architecture is shown infigure 1. Here only one processing unit is presentin the chip for performing the arithmetic or logical operations. At any particular time, onlyone operation can be performed.
Figure 1:
Single core CPU chip
 B. Simultaneous multithreading (SMT)architecture
SMT permits simultaneous multiple independentthreads to execute simultaneously on the samecore. If one thread is waiting for a floating pointoperation to complete, another thread can useinteger units. Without SMT, only a single threadcan run at any given time. But in SMT, the samefunctional unit cannot be executedsimultaneously. If two threads want to executethe integer unit at the same time, it is not possible with SMT. Here all the caches of thesystem are shared.
 . Chip Multi-Processor architecture
(IJCSIS) International Journal of Computer Science and Information Security,Vol. 8, No. 7, October 2010112http://sites.google.com/site/ijcsis/ISSN 1947-5500
 
In multi-core or chip multi-processor architecture, multiple processing units or chipsare present on a single die. Figure 2 shows amulti-core architecture with 3 cores in a singleCPU chip. Here all the cores are fit on a single processor socket called as Chip Multi Processor.The cores can run in parallel. Within each core,threads can be time-sliced similar to single processor system [17].
Figure 2:
Chip multi-processor architecture
The multi-core architecture with cache and mainmemory is shown in Figure 3, comprises processor cores from 0 to N and each core has private L1 cache which consists of instructioncache (I-cache) and date cache (D-cache).
Figure 3:
Multi-core architecture withmemory
Each L1 cache is connected to the shared L2cache. The L2 cache is unified and inclusive, i.e.it includes all the lines contained in the L1caches. The main memory is connected to L2cache, if the data requests are missed in L2cache, the data access will happened in mainmemory [20].
IV. EXISTING ENVIRONMENTS FOR CHIP MULTI- PROCESSOR ARCHITECTURE
The chip multi-processors are used in the rangeof desktop to high performance computingenvironments. The section 4.1 and section 4.2will show the existence and the main role of CMPs in various computing environments.
 A. High Performance Computing 
High performance computing uses supecomputers and computer clusters to solveadvanced computation problems. A list of themost powerful high-performance computers can be found on the Top500 list.Top500 is a list of the world’s fastest computers.The list is created twice a year and includessome rather large systems. Not all Top500systems are clusters, but many of them are builtfrom the same technology. There may be HPCsystems out there that are proprietary or notinterested in the Top500 ranking. The Top500list is the wealth of historical data. The list wasstarted in 1993 and has data on vendors,organizations, processors, memory, and so on for each entry in the list [22]. As per the informationtaken at June 2010 from [23], the first 10systems are given in the table 1.Table 1: Top 10 Super computers listRankProcessor detailsYea1.Jaguar - Cray XT5-HEOpteron Six Core 2.6GHz.2009.2.Nebulae - DawningTC3600 Blade, IntelX5650, NVidia TeslaC2050 GPU.2010.3.Roadrunner -BladeCenter QS22/LS21Cluster, PowerXCell 8i3.2 GHz / Opteron DC1.8 GHz, VoltaireInfiniband.2009.4.Kraken XT5 - Cray XT5-HE Opteron Six Core 2.6GHz.2009.5.JUGENE - Blue Gene/PSolution.2009.6.Pleiades - SGI Altix ICE8200EX/8400EX, XeonHT QC 3.0/Xeon2010.
(IJCSIS) International Journal of Computer Science and Information Security,Vol. 8, No. 7, October 2010113http://sites.google.com/site/ijcsis/ISSN 1947-5500

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/*********** DO NOT ALTER ANYTHING BELOW THIS LINE ! ************/ var s_code=s.t();if(s_code)document.write(s_code)//-->