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SEQUENTIAL
LOGIC
CIRCUITS
NISHA PRAKASH
ADE (EEC 309)
Boolean Algebra/Logic Circuits
Why are they called “logic circuits”?
Logic: The study of the principles of
reasoning.
The 19th Century Mathematician,
George Boole, developed a math
system (algebra) involving logic,
Boolean Algebra.
His variables took on TRUE, FALSE
Later Claude Shannon (father of
information theory) showed (in his
Master’s thesis!) how to map Boolean
Algebra to digital circuits: like gates
(AND, OR NOT,ETC)
An Introduction to Digital Logic
Integrated Circuits
The building blocks of computers
Designed for specialized functions
Examples: the CPU, bus interface, memory
management unit
Boolean logic
Rules for handling Boolean constants and
variables
3 fundamental operations:
combinations
LOGIC GATES
DIGITAL LOGIC
COMBINATIONAL
SEQUENTIAL
LOGIC
LOGIC
Digital systems
current input
Sequential
Inputs Outputs
Combinational circuit
“n” “m”
Input Output
variables variables
Logic gates
Examples:
ADDERS(BINARY, BCD)
SUBTRACTOR
MULTIPLEXER/DEMULTIPLEXER
DECODER/ENCODER
MAGNITUDE COMPARATOR
CONVERTERS(ALL SORT)
BINARY MULTIPLIERS
If S=1, Y=I1
Select the Source Register - The source register may
be selected by a Multiplexer circuit. (One multiplexer
per bit).
A 4-to-1 line MUX : Each of four inputs, I0 through I3
applied to one of input of AND gate. Selection lines S1
and S0 are decoded to select a particular AND gate.
The output of AND gate are applied to OR gate that
provides the 1-line output.
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
Example of a Combinatorial Circuit:
A Multiplexer (MUX)
m Inputs: I , I , I , ................ I
0 1 2 (m-1)
one Output: Y
n Control inputs: S0, S1, S2, ...... S(n-1)
One (or more) Enable input(s)
I0
2n inputs I1 Y
I2
1 output
I3
Enable S0 S1
(G) n control inputs
Characteristic Table of a Multiplexer
Y(Sn-1 ….. S1S0) = Σ(minterms)
Example: Implement the function
F (A, B, C) = ∑(1, 3, 5, 6)
This circuit uses the same AND gates and the same addressing
scheme as the two-input multiplexer circuit .
The basic difference is that it is the inputs that are combined
and the outputs that are separate. By making this change, we
get a circuit that is the inverse of the two-input multiplexer.
DECODER/ENCODER
What is a decoder ?
In older days, the (good) printers used be like typewriters:
– To print “A”, a wheel turned, brought the “A” key up, which
then was struck on the paper.
• Letters are encoded as 8 bit codes inside the computer.
– When the particular combination of bits that encodes “A” is
detected, we want to activate the output line corresponding
to A (Not actually how the wheels worked)
• How to do this “detection” : decoder
• General idea: given a k bit input,
– Detect which of the 2^k combinations is represented
– Produce 2^k outputs, only one of which is “1”.
What a decoder does ?
A n-to-2n decoder takes an n-bit input and produces 2n
outputs. The n inputs represent a binary number that
determines which of the 2n outputs is uniquely true.
A 2-to-4 decoder operates according to the following truth
table:
The 2-bit input is called SIS0 (serial in, serial out) and the
four outputs are Q0-Q3.
If the input is the binary number i, then output Qi is
uniquely true.
Follow the design procedures from last time! We have a
For a decoder,
EN=1 activates the decoder, so it behaves as specified
rebuilding the decoder from scratch every time you need it.
A Decoder is a Demultiplexer with a
change in the name of the inputs :
Y0
2 to 4
Decoder
Y1
ENABLE
INPUT Y2
Y4
S1 S0
When the IC is used as a Decoder, the input I is called
an Enable input
SEQUENTIAL
CIRCUITS
Properties of Sequential Circuits
input variables.
Here we will look at Sequential Logic circuits
The output(s) can depend on present and also past values of
Next
State State
Inputs Outputs
Combinational
Circuit
Flip-Flop
Clock pulses
Clock pulses
Synchronous
– the timing of all state transitions is controlled by a
common clock
– changes in all variables occur simultaneously
Asynchronous
– state transitions occur independently of any clock
and normally dependent on the timing of transitions
in the input variables
– changes in more than one output do not
necessarily occur simultaneously
Clock
– A clock signal is a square wave of fixed frequency
– Often, transitions will occur on one of the edges of
clock pulses i.e. the rising edge or the falling edge
Latches
In the same way that gates are the building blocks
of combinatorial circuits,
latches and flip-flops are the building blocks of
sequential circuits.
While gates had to be built directly from
transistors, latches can be built from gates, and
flip-flops can be built from latches.
This fact will make it somewhat easier to
understand latches and flip-flops!
• The difference between a latch and a flip-
flop is that a latch does not have a clock signal,
whereas a flip-flop always does.
adding inverter Q Q
to clock input.
C
C C
Q R
Q changes to the value on D applied at the positive clock edge within timing constraints to be specified. Q Q
Our choice as the standard flip-flop for most sequential circuits
Standard Symbols for Storage
Elements S S D D
R R C C
indicators C C
R R C C
indicator
C C
Triggered D Triggered D
(c) Edge-Triggered Flip-Flops
Other Flip-Flop Types
J-K and T flip-flops
Behavior
Implementation
Excitation tables
J-K Flip-flop
Behavior
Same as S-R flip-flop with J analogous to S and K
analogous to R
Except that J = K = 1 is allowed, and
For J = K = 1, the flip-flop changes to the opposite
state
As a master-slave, has same “1s catching” behavior
as S-R flip-flop
If the master changes to the wrong state, that state
will be passed to the slave
E.g., if master falsely set by J = 1, K = 1 cannot
J D
K
C
T (Toggle)Flip-flop
Behavior
Has a single input T
For T = 0, no change to state
For T = 1, changes to opposite state
Same as a J-K flip-flop with J = K = T
As a master-slave, has same “1s
catching” behavior as J-K flip-flop
Cannot be initialized to a known state
using the T input
Reset (asynchronous or synchronous)
essential
T Flip-flop Symbol
Implementation
To avoid 1s catching T
behavior, one solution
used is to use an
edge-triggered D as
the core of the flip-flop C
D
T
C
Basic Flip-Flop Descriptors
Used in analysis
Characteristic table - defines the next state
of the flip-flop in terms of flip-flop inputs
and current state
Characteristic equation - defines the next
state of the flip-flop as a Boolean function of
the flip-flop inputs and the current state
Used in design
Excitation table - defines the flip-flop input
variable values as function of the current
state and next state
D Flip-Flop Descriptors
Characteristic Table
D Q(t + 1) Operation
0 0 Reset
1 1 Set
Characteristic Equation
Q(t+1) = D
Excitation Table
Q(t +1) D Operation
0 0 Reset
1 1 Set
D-type Flip-Flop
D = input
Q = output signal
Q’ = NOT(Q)
CK = clock signal
0 Q(t) No change
1 Q(t) Complement
Characteristic Equation
Q(t+1) = T Q
Q(t) 0 No change
Q(t) 1 Complement
S-R Flip-Flop Descriptors
Characteristic Table S R Q(t +1) Operation
0 0 Q(t) No change
0 1 0 Reset
1 0 1 Set
1 1 ? Undefined
Characteristic Equation
Q(t+1) = S + R Q, S.R = 0 Q(t) Q(t+ 1) S R Operation
0 0 Q(t) No change
0 1 0 Reset
1 0 1 Set
1 1 Q(t) Complement
Characteristic Equation
Q(t+1) = J Q + K Q Q(t) Q(t +1) J K Operation
0 0 0 X No change
0 1 1 X Set
Excitation Table 1 0 X 1 Reset
1 1 X 0 No Change
ANALYSIS OF CLOCKED
SEQUENTIAL CIRCUITS
State Diagrams
The sequential circuit function can be
represented in graphical form as a state
diagram with the following components:
A circle with the state name in it for each state
A directed arc from the Present State to the Next
State for each state transition
A label on each directed arc with the Input values
which causes the state transition, and
A label:
On each circle with the output value produced, or
produced.
State Diagrams
Label form:
On circle with output included:
state/output
Moore type output depends only on state
On directed arc with the output
included:
input/output
Mealy type output depends on state and
input
Sequential circuits
Circuits that include flip-flops are usually classified
by the function they perform rather than by the
name of the sequential circuits.
Counters
Registers Counters
A register is a group of A counter is a register
flip-flops. that goes through
Each flip-flop is capable predetermined sequence
of storing 1 bit of of states.
information. A Counter is a special
An n-bit register type of register.
consists of n-flip-flops An n-bit counter consists
capable of storing n-bit of n-flip-flops and can
of binary information. count in binary from 0 to
2n-1.
REGISTERS
A flip-flop stores one bit of information
• When a set of n flip-flops is used to store n - bits of
data, we refer to these flip-flops as a Register
Common register usages include
• Holding a data value output from an arithmetic
circuit.
• Holding a count value in a counter circuit.
A common clock signal is typically used for each
flip-flop in a register.
Serial data transfer
One application of shift registers is converting between
“serial data” and “parallel data.”
Q0Q1Q2Q3 = 0100
Q0Q1Q2Q3 = 1010
Q0Q1Q2Q3 = 1101
Example – Shift left register
Assume a data word to be 1101.
Such that Q0Q1Q2Q3 = 1101
Q0Q1Q2Q3 = 0011
Q0Q1Q2Q3 = 0110
Q0Q1Q2Q3 = 1101
For this kind of register, data bits are entered
serially in the same manner as discussed in the last
section.
RIPPLE
RIPPLE SYNCHRONOUS
SYNCHRONOUS
(ASYNCHRONOUS)
(ASYNCHRONOUS) COUNTERS
COUNTERS
COUNTERS
COUNTERS
RIPPLE COUNTER SYNCHRONOUS COUNTER
The FF o/p transition The C i/p of all the FFs
act as source of receives a common clock.
triggering other FF.
(that means FF is not Therefore, they are
triggered by a synchronized only by a
common clock rather single clock.
by the o/p transition Faster response than
that occur in other
FFs). asynchronous counters
This form of counter
is slow
Binary count sequence
If we examine a four-bit
binary count sequence
from 0000 to 1111, a
definite pattern will be
evident in the
"oscillations" of the bits
between 0 and 1:
Note how the least significant bit (LSB) toggles
between 0 and 1 for every step in the count
sequence, while each succeeding bit toggles at
one-half the frequency of the one before it.
The most significant bit (MSB) only toggles
once during the entire sixteen-step count
sequence: at the transition between 7 (0111)
and 8 (1000).
Rising-edge and falling-edge clock inputs
Counting occurs when the clock input changes
state.
Most synchronous counters count on the
rising-edge which is the low to high
transition of the clock signal.
Most ripple counters count on the falling-
edge which is the high to low transition of the
clock signal.
2-bit Asynchronous(Ripple) counter
11 01
10
Usually, all the CLEAR inputs are connected together,
so that a single pulse can clear all the flip-flops
before counting starts.
The clock pulse fed into FF0 is rippled through the
other counters after propagation delays, like a ripple
on water, hence the name Ripple Counter.
The 2-bit ripple counter circuit above has four
different states, each one corresponding to a count
value. Similarly, a counter with n flip-flops can have
2 to the power n states. The number of states in a
counter is known as its mod (modulo) number. Thus
a 2-bit counter is a mod-4 counter.
A mod-n counter may also described as a divide-by-n
counter. This is because the most significant flip-flop
(the furthest flip-flop from the original clock pulse)
produces one pulse for every n pulses at the clock
input of the least significant flip-flop (the one
triggers by the clock pulse). Thus, the above counter
is an example of a divide-by-4 counter.
The following is a 3-bit asynchronous binary counter
and its timing diagram for one cycle. It works exactly
the same way as a two-bit asynchronous binary counter
mentioned above, except it has eight states due to the
third flip-flop.
000
001
111
010
110
011
101
100
1100
0011
1011
0100
1010
0101
1001 0110
1000 0111
• 4-bit asynchronous binary counter is also
called MOD-16 counter and Divide- by-16
counter.
• Because of the frequency of the last FF is equal
to the clock frequency 16.