COMBINATIONAL &

SEQUENTIAL
LOGIC
CIRCUITS

NISHA PRAKASH
ADE (EEC 309)
 Boolean Algebra/Logic Circuits
 Why are they called “logic circuits”?
 Logic: The study of the principles of
reasoning.
 The 19th Century Mathematician,
George Boole, developed a math
system (algebra) involving logic,
Boolean Algebra.
 His variables took on TRUE, FALSE
 Later Claude Shannon (father of
information theory) showed (in his
Master’s thesis!) how to map Boolean
Algebra to digital circuits: like gates
(AND, OR NOT,ETC)
 An Introduction to Digital Logic

 Integrated Circuits
 The building blocks of computers
 Designed for specialized functions
 Examples: the CPU, bus interface, memory

management unit

 Transistors: primary components of ICs

 Motorola MPC 7400 PowerPC modules: 6.5

million transistors in less than ½ in2

 Transistors
 Boolean algebra: basis for computer logic design

 Transistors: means for implementing Boolean

algebra
 Switches: on/off to represent the 0’s and 1’s of

binary digital circuits

 Combined to form logic gates
 Digital Circuits
 Combinatorial logic
 Results of an operation depend only on the

present inputs to the operation

 Uses: perform arithmetic, control data movement,

compare values for decision making

 Sequential logic
 Results depend on both the inputs to the

operation and the result of the previous operation

 Uses: counter
 Boolean Algebra

 Rules that govern constants and variables that can

take on 2 values
 True/false; on/off; yes/no; 0/1

 Boolean logic
 Rules for handling Boolean constants and

variables
 3 fundamental operations:

AND, OR and NOT

 Truth Table: specifies results for all possible input

combinations
LOGIC GATES
 DIGITAL LOGIC

COMBINATIONAL
SEQUENTIAL
LOGIC
LOGIC
 Digital systems

 A digital system is a system whose

inputs and outputs fall within a
discrete, finite set of values
 Two main types
 Combinational

 Outputs dependent only on

current input
 Sequential

 Outputs dependent on both

past and present inputs

 Combinational or Sequential?

 A circuit is combinatorial if and only if its output

depends exclusively on its input:
Out = fn (In)
 A circuit is sequential otherwise, that is, if its
output depends on some internal state (and
possibly on the input too):
Out = fn (In, State)
 Having a “state” means that the circuit has a
“memory”
A circuit made of gates (AND, OR, XOR, etc.)
without any loop is guaranteed to be
combinatorial
 Block diagram-Combinational circuits

 This circuit consists of logic gates whose outputs at any time

are determined from the present combinations of inputs.

Inputs Outputs
Combinational circuit
“n” “m”

 A combinational circuit performs an operation that can be

specified logically by a set of Boolean functions.
 Combinational
circuit

Input Output
variables variables
Logic gates
Examples:

 ADDERS(BINARY, BCD)
 SUBTRACTOR
 MULTIPLEXER/DEMULTIPLEXER
 DECODER/ENCODER
 MAGNITUDE COMPARATOR
 CONVERTERS(ALL SORT)
 BINARY MULTIPLIERS

ANY BOOLEAN FUNCTION CAN BE IMPLEMENTED BY THE

COMBINATIONAL CIRCUITS.
Need for multiplexing?
 Multiplexer
 A MULTIPLEXER is a combinational circuit that selects binary
information from one of many input lines and directs it to a
single output line.

 The selection of a particular input line is controlled by a set of

selection lines.

 Normally, there are 2n input lines and n- selection lines whose

bit combination determines which part is selected.
 A 2-to-1 line MUX connects one of two 1-bit sources to a
common destination as shown:

 A MUX acts like a switch that selects one of two sources.

 If S=0, Y=I0

 If S=1, Y=I1
 Select the Source Register - The source register may
be selected by a Multiplexer circuit. (One multiplexer
per bit).
 A 4-to-1 line MUX : Each of four inputs, I0 through I3
applied to one of input of AND gate. Selection lines S1
and S0 are decoded to select a particular AND gate.
The output of AND gate are applied to OR gate that
provides the 1-line output.

S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
 Example of a Combinatorial Circuit:
A Multiplexer (MUX)

Consider an integer ‘m’, which is

constrained by the following relation:
m = 2n , where m and n are
both integers.
 A m-to-1 Multiplexer has

 m Inputs: I , I , I , ................ I
0 1 2 (m-1)
 one Output: Y
 n Control inputs: S0, S1, S2, ...... S(n-1)
One (or more) Enable input(s)


such that Y may be equal to one of the inputs, depending upon

the control inputs.
 Example: A 4-to-1 Multiplexer
A 4-to-1 Multiplexer:

I0

2n inputs I1 Y
I2
1 output
I3

Enable S0 S1
(G) n control inputs
 Characteristic Table of a Multiplexer

 If the MUX is enabled,

s0 s1
0 0 Y=I0
0 1 Y=I1
1 0 Y=I2
1 1 Y=I3

Putting the above information in the form of a Boolean equation,

Y = S1’.S0’.I0 + S1’.S0.I1 + S1.S0’.I2 + S0.S1.I3
 A multiplexer is also called DATA SELECTOR, it selects
one of many inputs and steers the binary information to
the output lines.

8-to-1 line MUX

16-to-1
line
MUX
 Implementing Boolean Function using
Multiplexer

 METHOD 1 : Using a Mux with n-select inputs ‘n’ variables

need to be connected to ‘n’ select inputs. For a MUX with ‘n
‘select inputs, the output Y is given by:
 The MUX output expression is a SUM of minterms
expression for all minterms (mi) which have their
corresponding inputs (Di) equal to 1.

 Thus, it is possible to implement any function of n-

variables using a MUX with n-select inputs by proper
assignment of the input values (Di €{0 , 1}).


Y(Sn-1 ….. S1S0) = Σ(minterms)
 Example: Implement the function
F (A, B, C) = ∑(1, 3, 5, 6)

 Since number of variables n = 3, this requires a MUX with 3

select inputs, i.e. an 8x1 MUX.

 The most significant variable A is connected to the most

significant select input S2 while the least significant variable C
is connected to the least significant select input S0 ,
 Thus: S2 = A, S1 = B, and S0 = C

 For the MUX output expression (sum of minterms) to include

minterm 1 we assign D1 =1

 Likewise, to include minterms 3, 5, and 6 in the sum of

minterms expression while excluding minterms 0, 2, 4, and 7,
the following input (Di) assignments are made.
S2(A) S1(B) S0(C) D(output)
0 0 0 D0=0
0 0 1 D1=1
0 1 0 D2=0
0 1 1 D3=1
1 0 0 D4=0
1 0 1 D5=1
1 1 0 D6=1
1 1 1 D7=0
D1 = D3 = D5 = D6 = 1
D0 = D2 = D4 = D7 = 0
 METHOD 2 : Using a MUX with (n-1) select inputs

 Any n-variable logic function can be implemented using a Mux

with only (n-1) select inputs (e.g 4-to-1 mux to implement any
3 variable function)

 This can be accomplished as follows:

 Express function in canonical sum-of-minterms form.
 Choose n-1 variables to be connected to the mux select
lines.
 Construct the truth table of the function, but grouping the
n-1 select input variables together (e.g. by making the n-1
select variables as most significant inputs).

 The values of Di (mux input line) will be 0, or 1, or nth variable

or complement of nth variable of value of function F, as will be
clarified by the following example.
 Example : Implement the function
F (A, B, C) = Σ (1, 2, 6, 7)

 This function can be implemented with a 4-to-1 line MUX.

a) The first (n-1) variables of function are connected to selection
inputs of MUX.
b) The remaining single variable of the function is used for data
inputs. If the single variable is denoted by C, each data input of
MUX will be C, C’, 1 or 0.

 a) => A and B are applied to the select line,

that is A => S1
B => S0
b) => C is 0 and 1

 The truth table of the function and the implementation are as

shown:
 DEMUX

 It is a digital function that performs inverse of the

multiplexing operation.

 It has one input line (E) and transmits it to one of

2n possible output lines (D0, D1, D2, …,D2n-1).

 The selection of the specific output is controlled by

the bit combination of n select inputs.
 Example : A 1-to-2 line Demux

 This circuit uses the same AND gates and the same addressing
scheme as the two-input multiplexer circuit .
 The basic difference is that it is the inputs that are combined
and the outputs that are separate. By making this change, we
get a circuit that is the inverse of the two-input multiplexer.
 DECODER/ENCODER
 What is a decoder ?
 In older days, the (good) printers used be like typewriters:

– To print “A”, a wheel turned, brought the “A” key up, which
then was struck on the paper.
• Letters are encoded as 8 bit codes inside the computer.
– When the particular combination of bits that encodes “A” is
detected, we want to activate the output line corresponding
to A (Not actually how the wheels worked)
• How to do this “detection” : decoder
• General idea: given a k bit input,
– Detect which of the 2^k combinations is represented
– Produce 2^k outputs, only one of which is “1”.
 What a decoder does ?
 A n-to-2n decoder takes an n-bit input and produces 2n
outputs. The n inputs represent a binary number that
determines which of the 2n outputs is uniquely true.
 A 2-to-4 decoder operates according to the following truth
table:
 The 2-bit input is called SIS0 (serial in, serial out) and the
four outputs are Q0-Q3.
 If the input is the binary number i, then output Qi is
uniquely true.
 Follow the design procedures from last time! We have a

truth table, so we can write equations for each of the four

outputs (Q0-Q3), based on the two inputs (S0-S1).
 Enable inputs
 Many devices have an additional enable input, which is used to
“activate” or “deactivate” the device.

 For a decoder,
 EN=1 activates the decoder, so it behaves as specified

earlier. Exactly one of the outputs will be 1.

 EN=0 “deactivates” the decoder. By convention, that means

all of the decoder’s outputs are 0.

 We can include this additional input in the decoder’s truth table:

 In this table, note that whenever
EN=0, the outputs are always 0,
regardless of inputs S1 and S0.

 We can abbreviate the table by

writing X’s in the input columns
for S1 and S0.
 Blocks and abstraction

 Decoders are common enough that we want to encapsulate

them and treat them as an individual entity.
 Block diagrams for 2-to-4 decoders are shown here. The names
of the inputs and outputs, not their order, is what matters.

 A decoder block provides abstraction:

 You can use the decoder as long as you know its truth table

or equations, without knowing exactly what’s inside.

 It makes diagrams simpler by hiding the internal circuitry.

 It simplifies hardware reuse. You don’t have to keep

rebuilding the decoder from scratch every time you need it.
 A Decoder is a Demultiplexer with a
change in the name of the inputs :

Y0
2 to 4
Decoder
Y1
ENABLE

INPUT Y2

Y4

S1 S0
When the IC is used as a Decoder, the input I is called
an Enable input
SEQUENTIAL
CIRCUITS
 Properties of Sequential Circuits

 So far we have seen Combinational Logic

 The output (s) depends only on the current values of the

input variables.
 Here we will look at Sequential Logic circuits
 The output(s) can depend on present and also past values of

the input and the output variables

 Sequential circuits exist in one of a defined number of states at
any one time
 they move "sequentially" through a defined sequence of

transitions from one state to the next

 The output variables are used to describe the state of a
sequential circuit either directly or by deriving state variables
from them.
 LATCHES
 FLIP-FLOPS:-
 S-R FLIP-FLOP
 J-K FLIP-FLOP
 T FLIP-FLOP
 D FLIP-FLOP
 Sequential logic devices set their outputs based on
timing and/or history of the state of the inputs or
stored data bits.
 The trigger signal is called the clock (CK or CP)
signal and it changes the state of the outputs based
on a positive edge or negative edge of CK and the
status of stored data bits.
 Outputs
Inputs Combinational
Logic
Storage
Elements

Next
State State
Inputs Outputs
Combinational
Circuit

Flip-Flop

Clock pulses

Clock pulses
 Synchronous
– the timing of all state transitions is controlled by a
common clock
– changes in all variables occur simultaneously
 Asynchronous
– state transitions occur independently of any clock
and normally dependent on the timing of transitions
in the input variables
– changes in more than one output do not
necessarily occur simultaneously
Clock
– A clock signal is a square wave of fixed frequency
– Often, transitions will occur on one of the edges of
clock pulses i.e. the rising edge or the falling edge
 Latches
 In the same way that gates are the building blocks
of combinatorial circuits,
 latches and flip-flops are the building blocks of
sequential circuits.
 While gates had to be built directly from
transistors, latches can be built from gates, and
flip-flops can be built from latches.
 This fact will make it somewhat easier to
understand latches and flip-flops!
 • The difference between a latch and a flip-
flop is that a latch does not have a clock signal,
whereas a flip-flop always does.

 How can we make a circuit out of gates that is

not combinatorial?

 The answer is feed-back, which means that we

create loops in the circuit diagrams so that output
values depend, indirectly, on themselves.
 Basic (NOR) S–R Latch
R (reset)
Q
 Cross-
coupling two
NOR gates
S (set) Q
gives S-R
Latch
Time R S Q Q Comment
0 0 ? ? Stored state unknown
0 1 1 0 “Set” Q to 1
0 0 1 0 Now Q “remembers” 1
1 0 0 1 “Reset” Q to 0
0 0 0 1 Now Q “remembers” 0
1 1 0 0 Both go low
0 0 ? ? Unstable!
 Time R S Q Q Comment
0 0 ? ? Stored state unknown
0 1 1 0 “Set” Q to 1
0 0 1 0 Now Q “remembers” 1
1 0 0 1 “Reset” Q to 0
0 0 0 1 Now Q “remembers” 0
1 1 0 0 Both go low
0 0 ? ? Unstable!
The
waveform
shows the
operation of
NOR gates
based RS
Latch.
 Basic (NAND) S-R Latch
S (set)
Q
 “Cross-Coupling”

two NAND R (reset) Q

gates gives
Time R S Q Q Comment
the S-R Latch 1 1 ? ? Stored state unknown
 S = 0, R = 0 is 1 0 1 0 “Set” Q to 1
1 1 1 0 Now Q “remembers” 1
forbidden as
0 1 0 1 “Reset” Q to 0
input pattern
1 1 0 1 Now Q “remembers” 0
0 0 1 1 Both go high
1 1 ? ? Unstable!
 Clocked S-R Latch
S
Q
 Adding two NAND
gates to the basic C
S-R NAND latch
Q
gives the clocked R
S–R latch:

 Has a time sequence behavior similar to the basic S-R latch

except that the S and R inputs are only observed when the
line C is high.
 C means “control” or “clock”.
 Clocked (Gated) S-R Latch
 The Clocked S-R Latch can be described by a table
S
Q Q(t) S R Q(t+1) Comment
C 0 0 0 0 No change
Q 0 0 1 0 Clear Q
R
0 1 0 1 Set Q
 The table describes 0 1 1 ??? Indeterminate
what happens after the 1 0 0 1 No change
clock [at time (t+1)] 1 0 1 0 Clear Q
based on: 1 1 0 1 Set Q
 current inputs (S,R) and 1 1 1 ??? Indeterminate
 current state Q(t).
 D Latch D
Q
 Adding an inverter
C
to the S-R Latch,
gives the D Latch: Q
 Note that there are
no “indeterminate” The graphic symbol for a
states! D Latch is:
Q D Q(t+1) Comment
D Q
0 0 0 No change
0 1 1 Set Q
1 0 0 Clear Q C Q
1 1 1 No Change
It is also called “Transparent Latch”
Flip-Flops
 Master-slave flip-flop
 Edge-triggered flip-flop
 Standard symbols for storage
elements
 S-R Master-Slave Flip-Flop
S S Q S Q Q
 Two clocked C C C
S-R latches in series R R Q R Q Q
with the clock on the
second latch inverted
 The input is observed
by the first latch with C = 1
 The output is changed by the second latch with C = 0
 The path from input to output is broken by the
difference in clocking values (C = 1 and C = 0).
 The behavior demonstrated by the example with D
driven by Y given previously is prevented since the clock
must change from 1 to 0 before a change in Y based on
D can occur.
 Edge-Triggered D Flip-Flop
D D Q S Q Q
C
 The edge-triggered
C C
D flip-flop is the Q R Q Q
same as the master-
slave D flip-flop
 It can be formed by:
 Replacing the first clocked S-R latch with a clocked D latch or
 Adding a D input and inverter to a master-slave S-R flip-flop
 The delay of the S-R master-slave flip-flop can be avoided
since the 1s-catching behavior is not present with D replacing
S and R inputs
 The change of the D flip-flop output is associated with the
negative edge at the end of the pulse
 It is called a negative-edge triggered flip-flop
 Positive-Edge Triggered D
Flip-Flop
Formed by D D Q S


adding inverter Q Q
to clock input.
C
C C
 Q R
Q changes to the value on D applied at the positive clock edge within timing constraints to be specified. Q Q
 Our choice as the standard flip-flop for most sequential circuits
 Standard Symbols for Storage
Elements S S D D

R R C C

SR SR D with 1 Control D with 0 Control

(a) Latches
 Master-Slave:
Postponed output S S D D

indicators C C
R R C C

Triggered SR Triggered SR Triggered D Triggered D

(b) Master-Slave Flip-Flops
 Edge-Triggered:
Dynamic D D

indicator
C C

Triggered D Triggered D
(c) Edge-Triggered Flip-Flops
 Other Flip-Flop Types
 J-K and T flip-flops
 Behavior
 Implementation

 Basic descriptors for understanding

and using different flip-flop types
 Characteristic tables
 Characteristic equations

 Excitation tables
 J-K Flip-flop
 Behavior
 Same as S-R flip-flop with J analogous to S and K
analogous to R
 Except that J = K = 1 is allowed, and
 For J = K = 1, the flip-flop changes to the opposite
state
 As a master-slave, has same “1s catching” behavior
as S-R flip-flop
 If the master changes to the wrong state, that state
will be passed to the slave
 E.g., if master falsely set by J = 1, K = 1 cannot

reset it during the current clock cycle

 J-K Flip-flop  Symbol
 Implementation
 To avoid 1s catching
behavior, one solution J
used is to use an
edge-triggered D as C
the core of the flip-flop
K

J D

K
C
 T (Toggle)Flip-flop
 Behavior
 Has a single input T
 For T = 0, no change to state
 For T = 1, changes to opposite state
 Same as a J-K flip-flop with J = K = T
 As a master-slave, has same “1s
catching” behavior as J-K flip-flop
 Cannot be initialized to a known state
using the T input
 Reset (asynchronous or synchronous)
essential
 T Flip-flop  Symbol

 Implementation
 To avoid 1s catching T
behavior, one solution
used is to use an
edge-triggered D as
the core of the flip-flop C

D
T

C
 Basic Flip-Flop Descriptors
 Used in analysis
 Characteristic table - defines the next state
of the flip-flop in terms of flip-flop inputs
and current state
 Characteristic equation - defines the next
state of the flip-flop as a Boolean function of
the flip-flop inputs and the current state
 Used in design
 Excitation table - defines the flip-flop input
variable values as function of the current
state and next state
D Flip-Flop Descriptors
 Characteristic Table
D Q(t + 1) Operation

0 0 Reset
1 1 Set

 Characteristic Equation
Q(t+1) = D

 Excitation Table
Q(t +1) D Operation
0 0 Reset
1 1 Set
 D-type Flip-Flop

D = input
Q = output signal
Q’ = NOT(Q)
CK = clock signal

Q takes the value of D

when the CK signal is
active.
T Flip-Flop Descriptors
 Characteristic Table
T Q(t +1) Operation

0 Q(t) No change
1 Q(t) Complement

 Characteristic Equation
Q(t+1) = T  Q

 Excitation Table Q(t +1) T Operation

Q(t) 0 No change

Q(t) 1 Complement
 S-R Flip-Flop Descriptors
 Characteristic Table S R Q(t +1) Operation

0 0 Q(t) No change
0 1 0 Reset
1 0 1 Set
1 1 ? Undefined

 Characteristic Equation
Q(t+1) = S + R Q, S.R = 0 Q(t) Q(t+ 1) S R Operation

 Excitation Table 0 0 0 X No change

0 1 1 0 Set
1 0 0 1 Reset
1 1 X 0 No change
 J-K Flip-Flop Descriptors
 Characteristic Table J K Q(t+1) Operation

0 0 Q(t) No change
0 1 0 Reset
1 0 1 Set
1 1 Q(t) Complement

 Characteristic Equation
Q(t+1) = J Q + K Q Q(t) Q(t +1) J K Operation

0 0 0 X No change
0 1 1 X Set
 Excitation Table 1 0 X 1 Reset
1 1 X 0 No Change
ANALYSIS OF CLOCKED
SEQUENTIAL CIRCUITS
 State Diagrams
 The sequential circuit function can be
represented in graphical form as a state
diagram with the following components:
 A circle with the state name in it for each state
 A directed arc from the Present State to the Next
State for each state transition
 A label on each directed arc with the Input values
which causes the state transition, and
 A label:
 On each circle with the output value produced, or

 On each directed arc with the output value

produced.
 State Diagrams
 Label form:
 On circle with output included:

 state/output
 Moore type output depends only on state
 On directed arc with the output
included:
 input/output
 Mealy type output depends on state and
input
 Sequential circuits
 Circuits that include flip-flops are usually classified
by the function they perform rather than by the
name of the sequential circuits.

 Two such circuits are:

 Registers

 Counters
 Registers Counters
 A register is a group of  A counter is a register
flip-flops. that goes through
 Each flip-flop is capable predetermined sequence
of storing 1 bit of of states.
information.  A Counter is a special
 An n-bit register type of register.
consists of n-flip-flops  An n-bit counter consists
capable of storing n-bit of n-flip-flops and can
of binary information. count in binary from 0 to
2n-1.
 REGISTERS
 A flip-flop stores one bit of information
• When a set of n flip-flops is used to store n - bits of
data, we refer to these flip-flops as a Register
Common register usages include
• Holding a data value output from an arithmetic
circuit.
• Holding a count value in a counter circuit.
 A common clock signal is typically used for each

flip-flop in a register.
 Serial data transfer
 One application of shift registers is converting between
“serial data” and “parallel data.”

• Computers typically work with multiple-bit quantities.

– ASCII text characters are 8 bits long.
– Integers, single-precision floating-point numbers, and screen
pixels are up to 32 bits long.
• But sometimes it’s necessary to send or receive data serially,
or one bit at a time. Some examples include:
 Input devices such as keyboards and mice.
 Output devices like printers.
 Any serial port, USB device transfers data serially.
 Recent switch from Parallel ATA to Serial ATA in hard drives.
 Receiving serial data
 To receive serial data using a shift register:
– The serial device is connected to the register’s SI input.
– The shift register outputs Q3-Q0 are connected to the
computer.
• The serial device transmits one bit of data per clock cycle.
– These bits go into the SI input of the shift register.
– After four clock cycles, the shift register will hold a four-bit
word.
• The computer then reads all four bits at once from the Q3-Q0
outputs.
 Sending data serially
 To send data serially with a shift register, you do the
opposite:
– The CPU is connected to the register’s D inputs.
– The shift output (Q3 in this case) is connected to the
serial device.
• The computer first stores a four-bit word in the register,
in one cycle.
• The serial device can then read the shift output.
– One bit appears on Q3 on each clock cycle.
– After four cycles, the entire four-bit word will have been
sent.
 Shift register

 A register that provides the ability to shift its

contents by a single bit
 May be to the right or left (or possibly both)

Shift right register

Example: Basic four-bit shift register
A basic four-bit shift register can be constructed
using four D flip-flops, as shown in Figure.
 The operation of the circuit is as follows:

 The register is first cleared, forcing all four outputs

to zero.
 The input data is then applied sequentially to the D
input of the first flip-flop on the left (FF0).
 During each clock pulse, one bit is transmitted from
left to right.

 Assume a data word to be 1101.

 The least significant bit of the data has to be shifted
through the register from FF0 to FF3.
 Example – Shift right register
 Assume a data word to be 1101.
 Such that Q0Q1Q2Q3 = 1101
 Initially Q0Q1Q2Q3 = 0000
(all FF are reset by Clear pin)
 Data is entered from left side towards the right.

Data in Data out

Q0Q1Q2Q3 = 1000

Q0Q1Q2Q3 = 0100
 Q0Q1Q2Q3 = 1010

Q0Q1Q2Q3 = 1101
 Example – Shift left register
 Assume a data word to be 1101.
 Such that Q0Q1Q2Q3 = 1101

 Initially Q0Q1Q2Q3 = 0000

(all FF are reset by Clear pin)

 Data is entered from right most FF and o/p is taken

from left most FF.

Data out Data in

Q0Q1Q2Q3 = 0001

Q0Q1Q2Q3 = 0011
Q0Q1Q2Q3 = 0110

Q0Q1Q2Q3 = 1101
 For this kind of register, data bits are entered
serially in the same manner as discussed in the last
section.

 The difference is the way in which the data bits

are taken out of the register. Once the data are
stored, each bit appears on its respective output
line, and all bits are available simultaneously.

 A construction of a four-bit serial in - parallel

out register is shown.
 For parallel in - parallel out shift registers, all data bits appear
on the parallel outputs immediately following the
simultaneous entry of the data bits. The following circuit is a
four-bit parallel in - parallel out shift register constructed by D
flip-flops.
 Parallel-in, parallel-out
( universal shift register)
 A register capable of shifting in only one direction is a
Unidirectional shift register.
 One that shift in both direction is called Bidirectional
shift register.
 If a register has both shifts and parallel load
capabilities, it is referred to as Universal shift register.
 The purpose of the parallel-in/ parallel-out shift
register is to take in parallel data, shift it, then output
it as shown below. A universal shift register is a do-
everything device in addition to the parallel-in/
parallel-out function.
 Mode control
s1 s0 Register
operation
0 0 No change
0 1 Shift right
1 0 Shift left
1 1 Parallel load
The selection lines
(S1S0)controls the
Operation of the
register according the
function table
 Counters
 What is counter?
 Count 1,2,3………100 and back to 1,2…..
 A counter is a sequential logic circuit
capable of counting the number of clock
pulses arriving at its clock input.
 The sequence can be : ascending or
descending.
 A specified sequence of states appear at
the counter.
 Special purpose arithmetic circuits used for the
purpose of counting
 Design circuits that can increment or decrement a
count by 1
 Counter circuits serves many purposes
 Count occurrences of certain events
 Generate timing intervals for controlling various tasks
in a digital system
 Track elapsed time between events
 Often (but not always) built with T flip-flops because
the toggle feature is naturally suited for implementing
the counting operation
 A counter is set of flip-flops (FFs) whose states
changes in response to pulses applied at input.
 The pulses can be in the form of clock.
 A counter that follows the binary number sequence
is called Binary Counter.
 An n-bit counter consists of n- FFs and can count in
binary from 0 through 2n-1.
 They can be of two types : a) up-counter
(ascending)
b) down-counter
(descending)
 COUNTERS
COUNTERS

RIPPLE
RIPPLE SYNCHRONOUS
SYNCHRONOUS
(ASYNCHRONOUS)
(ASYNCHRONOUS) COUNTERS
COUNTERS
COUNTERS
COUNTERS
 RIPPLE COUNTER SYNCHRONOUS COUNTER
 The FF o/p transition  The C i/p of all the FFs
act as source of receives a common clock.
triggering other FF.
 (that means FF is not  Therefore, they are
triggered by a synchronized only by a
common clock rather single clock.
by the o/p transition  Faster response than
that occur in other
FFs). asynchronous counters
 This form of counter
is slow
Binary count sequence
If we examine a four-bit
binary count sequence
from 0000 to 1111, a
definite pattern will be
evident in the
"oscillations" of the bits
between 0 and 1:
          
 Note how the least significant bit (LSB) toggles
between 0 and 1 for every step in the count
sequence, while each succeeding bit toggles at
one-half the frequency of the one before it.
 The most significant bit (MSB) only toggles
once during the entire sixteen-step count
sequence: at the transition between 7 (0111)
and 8 (1000).
 Rising-edge and falling-edge clock inputs
 Counting occurs when the clock input changes
state.
 Most synchronous counters count on the
rising-edge which is the low to high
transition of the clock signal.
 Most ripple counters count on the falling-
edge which is the high to low transition of the
clock signal.
 2-bit Asynchronous(Ripple) counter

 A two-bit asynchronous counter is shown.

  The external clock is connected to the clock input
of the first flip-flop (FF0) only.  So, FF0 changes
state at the falling edge of each clock pulse, but FF1
changes only when triggered by the falling edge of
the Q output of FF0.  
 Because of the inherent propagation delay through
a flip-flop, the transition of the input clock pulse
and a transition of the Q output of FF0 can never
occur at exactly the same time.
  Therefore, the flip-flops cannot be triggered
simultaneously, producing an asynchronous
operation.
 State diagram
00

11 01

10
 Usually, all the CLEAR inputs are connected together,
so that a single pulse can clear all the flip-flops
before counting starts.
  The clock pulse fed into FF0 is rippled through the
other counters after propagation delays, like a ripple
on water, hence the name Ripple Counter.
 The 2-bit ripple counter circuit above has four
different states, each one corresponding to a count
value.  Similarly, a counter with n flip-flops can have
2 to the power n states.  The number of states in a
counter is known as its mod (modulo) number.  Thus
a 2-bit counter is a mod-4 counter.
 A mod-n counter may also described as a divide-by-n
counter.  This is because the most significant flip-flop
(the furthest flip-flop from the original clock pulse)
produces one pulse for every n pulses at the clock
input of the least significant flip-flop (the one
triggers by the clock pulse).  Thus, the above counter
is an example of a divide-by-4 counter.
 The following is a 3-bit asynchronous binary counter
and its timing diagram for one cycle.  It works exactly
the same way as a two-bit asynchronous binary counter
mentioned above, except it has eight states due to the
third flip-flop.
 000

001
111

010
110

011
101
100

3-bit asynchronous binary counter is also called

MOD-8 counter and Divide- by-8 counter
4-bit asynchronous binary
counter
“Ripple” counter (Mano)
 4-bit asynchronous binary counter is also
called MOD-16 counter and Divide- by-16
counter.
1111 0000
0001
1110 0010

1100
0011

1011
0100

1010
0101
1001 0110
1000 0111
• 4-bit asynchronous binary counter is also
called MOD-16 counter and Divide- by-16
counter.
• Because of the frequency of the last FF is equal
to the clock frequency 16.

• fD=f /16 ; fD = frequency of IVth FF

f = clock frequency
A common application is in machine motion control, where
devices called rotary shaft encoders convert mechanical
rotation into a series of electrical pulses, these pulses
"clocking" a counter circuit to track total motion: