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8086 - Microprocessor and Applications (AU-CBE, R2008)

8086 - Microprocessor and Applications (AU-CBE, R2008)

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Published by N.Shanmugasundaram
8086 microprocessor notes, Anna university-Coimbatore, R2008, Prepared by N.Shanmugasundaram, ECE dept, Vidyaa Vikas College of Engg & Technology
8086 microprocessor notes, Anna university-Coimbatore, R2008, Prepared by N.Shanmugasundaram, ECE dept, Vidyaa Vikas College of Engg & Technology

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Published by: N.Shanmugasundaram on Nov 04, 2010
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04/04/2013

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EC1303 Microprocessor & its applications Unit III
© NSS/ECE1
Intel 8086:
Features:
1.
 
16-bit Data bus2.
 
Computes 16 bit / 32 bit data.3.
 
20-bit address bus.4.
 
More memory addressing capability (2
20
= 1MB)5.
 
16 bit Flag register with 9 Flags6.
 
Can be operated in Minimum mode and Maximum mode7.
 
Has two stage pipelined architecture8.
 
No internal clock generation9.
 
40 pin DIP IC - HMOS technology10.
 
Operates on +5V supply voltage11.
 
Has more powerful instruction set
8086 PIN CONFIGURATION:
 
The 16-bit 8086 microprocessor has 40 pins.
 
It is available in 5 MH, 8MHz and 10 MHz.
 
It can operate in two modes, i.e. single processor (minimum mode) or multiprocessor(maximum mode) configuration.
 
The signals are categorized in three groups as follows(i) Common signal, which are used in minimum as well as maximum mode(ii) Signal for minimum mode(iii) Signals for maximum mode.
 
The pin diagram for 8086 processor is shown in fig.
Fig.1 – Pin diagram of 8086.
 
EC1303 Microprocessor & its applications Unit III
© NSS/ECE2
MINIMUM MODE CONFIGURATION OF 8086 SYSTEM:
When MN/MX (low) pin is in logic 1, the 8086 microprocessor operates in minimum modesystem. In this mode, the microprocessor chip itself gives out all the control signals.
 
This is a single processor mode.
 
The remaining components in the system are latches, transceivers, clock generator,memory or I/O devices.
 
The latches are used for separating the valid address from the multiplexed address/datasignals and the controlled by the ALE signal generated by 8086.
 
Transceivers are the bi-directional buffers. They are required to separate the valid datafrom the time multiplexed address/data signal. This is controlled by two signals, DEN& DT/R (low).
 
DT/R (low) indicates that the direction of data, i.e. from or to the indicator.
 
DEN signal indicates the valid data is available on the data bus.
 
The clock generator in the system is used to generate the clock and to synchronizesome external signals with the system clock.The minimum mode system organization is,
Fig. 2-Minimum mode of 8086 
 
EC1303 Microprocessor & its applications Unit III
© NSS/ECE3
MAXIMUM MODE CONFIGURATION OF 8086 SYSTEM:
If the MN/MX (low) pin is low i.e. zero, then the 8086 can operate in maximum mode. In thismode, the Bus controller (8288) chip used to generate control signals I/O W, I/O R, RD, WR(Active low) etc., by receiving the active low status signals (S
2
, S
1
& S
0
) from themicroprocessor.
 
MRDC (low) :
Memory read command – It instructs the memory to put the contents of the addressed location to the data bus.
 
MWTC (low) :
Memory write command – It instructs the memory to accept the dataon the data bus and load that data into the address memory location.
 
IORC (low) :
I/O read command – It instructs an I/O device to put the data containedin the addressed port on the data bus.
 
IOWC (low) :
I/O write command – It instructs an I/O device to accept the data on thedata bus and load the data into the addressed port.
 
AIOWC (low) / AMWC (low) :
Advance IO write command / Advance memory writecommand – These are similar to IOWC and MWTC except that they are activated oneclock pulse earlier. This gives slow interfaces an extra clock cycle to prepare to inputthe data.
 
 
This system also consists of latches, tristate buffer, memory input-output device, etc.
 
The DEN, DT/R, ALE, etc is derived by the bus controller from the informationavailable on the active low status signals (S
2
, S
1
& S
0
).
 
In this mode, Request/Grant pin (RQ/GT) is checked at each rising pulse of clock I/Pwhen the request is detected and if Hold request are satisfied, the processor issues agrant pulse over RQ/GT pin immediately during T4 or next T1 state to accept thecontrol of the bus. Therefore, the requesting controller uses the bus till it requires.
 
When it is ready to relinquish the bus, it sends a release pulse to the processor using theRQ/GT pin.The figure below shows 8086 processor in maximum mode.
Fig. 3-Maximum mode of 8086 

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/*********** DO NOT ALTER ANYTHING BELOW THIS LINE ! ************/ var s_code=s.t();if(s_code)document.write(s_code)//-->