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OptimizingFPGA-basedvectorproductdesigns
DanielBenyamin
1
,WayneLuk
2
,andJohnVillasenor
1 1
ElectricalEngineeringDepartment,UCLA,LosAngeles,CA,90095
f
benyamin,villa
g
@icsl.ucla.edu
2
DepartmentofComputing,ImperialCollege 180Queen'sGate,London,EnglandSW72BZ
Abstract
Thispaperpresentsamethod,calledmultiplecon- stantmultipliertreesMCMTs,forproducingopti- mizedrecongurablehardwareimplementationsofvec- torproducts.AnalgorithmforgeneratingMCMTs hasbeendevelopedandimplemented,whichisbased onanovelrepresentationofcommonsubexpressions inconstantdatapatterns.Ouroptimizationframe- workcoversawidersolutionspacethanpreviousap- proaches;italsosupportsexploitationoffullandpar- tialrun-timerecongurationaswellastechnology- specicconstraints,suchasfanoutlimitsandrouting. Wedemonstratethatwhiledistributedarithmetictech- niquesrequirestoragesizeexponentialinthenumber ofcoecients,theresourceutilizationofMCMTsusu- allygrowslinearlywithproblemsize.MCMTshave beenimplementedinXilinx4000andVirtexFPGAs, andtheirsizeandspeedeciencyareconrmedin comparisonswithXilinxLogiCoreandASICimple- mentationsofFIRlterdesigns.Preliminaryresults showthatthesizeofMCMTcircuitsislessthanhalf ofthatofcomparabledistributedarithmeticcores.
1Introduction
Thevectordotproductorsumofproducts"is oneofthemostcommonalgorithmickernelsinsignal processing.Itsuserangesfromltersandcorrelators tocompletetwo-dimensionalimagetransformssuchas theDiscreteCosineTransformDCT. The
mojave
ProjectatUCLA1hasshown thatFPGAscanbehighlyeectiveincomputing two-dimensionalcorrelationsusing1-bitaddertrees. Specically,theauthorsindicateanimportantwayof leveragingtherecongurabilityofFPGAs:anFPGA circuitdesignercanaordtoimplementcircuitsbased onparametersthatrarelyorneverchange;thesecir- cuitscanbedesignedveryecientlyduetotheavail- abilityof
apriori
knowledge.Variable-operandcir- cuitsarepreferredoverconstant-operandcircuitsin ASICdesigns,duetothehighnon-recurringengineer- ingcostrequiredtochangetheconstantoperands. Indeed,constant-operandcircuitsonlyndtheirway intoASICswhentheyarewidelyapplicable;the8x8 matrixofDCTcoecientsisonesuchexample. Unlesstheproblemsizeissmall,however,imple- mentingeectiveconstant-operandFPGAcircuitsby handcanbeverytedious.Thispaperpresentsa hardwareimplementationofvectorproductscalled multipleconstantmultipliertreesMCMTs.The coreoftheMCMTalgorithmisournovelrepresenta- tionofcommonsubexpressionscontainedinconstant datapatterns,whichprovidesforseveraloptimiza- tioncapabilitiesnotpresentinpreviousdesignstrate- gies.First,weadoptaglobaloptimizationstrategy tocoverawidesolutionspace,thusgeneratingsolu- tionsnotconsideredbypreviousapproaches.Second, ourmethodisabletoexploittherun-timerecong- urabilityofFPGAs,whichcanprofoundlyreducethe eectivecircuitsize.Third,technology-speciccon- straints,suchasfanoutlimitsandrouting,canbe takenintoaccountbyouroptimizationprocedure.
2OverviewandRelatedWork
Anumberofhardwareimplementationsexistfor computingvectorproducts.Therearestraightfor- warddesigns,wherethevectorproductiscomputed usingconstantcoecientmultipliersKCMsand adders.Othertechniques,suchasdistributedarith- meticDA,directlycomputevectorproductsinaless obviousmanner.Insection8weprovidecomparisons ofMCMTstoDAandothertraditionalarchitectures. Ourapproachistobreakdownmultipleconstants tothebitlevelandrepresenttheminamannerthat
isecientforoptimizingtherequirednumberofad- ditions.Whilemultiplicationswithaconstantvalue arecommonlyperformedusingshiftsandadditions, researchonthejointoptimizationofmultiplecon- stantsisrelativelynew.Potkonjak4presentsagen- eralizedsystemnamedmultipleconstantmultipliers MCMs.Thisapproachcanbeappliedtoanyprob- lemwhereanunknownismultipliedbymorethanone constantvalue,andcanoptimizeforboththenumber ofadditionsandthenumberofrequiredshifts.Fe- her6concentratesongeneratingvectorproductcir- cuitsforFPGAs,andappliesthetechniquestothe two-dimensionalDCT.Feher'sworkimplementsonly bit-serialdesigns,whichnotonlysimpliestheprob- lemofhighfanoutnodes,but,duetothenecessary parallel-serialconversion,isonlyofinterestwhenthe applicationcanaordalowthroughput.Furthermore, Feher'salgorithmutilizesapairwisegreedyapproach, whichprovidespoorresultsformanyproblemcases. Additionalworkincludesrecodingformultiplecoe- cients5andoptimizationsforDSParchitectures3. Thesetechniques,however,donotexploitthefullpo- tentialofFPGAs,especiallyinregardstorun-time recongurationRTR.
3ConstantMultiplierTrees
ForthispaperwewillapplytheMCMTtechnique toproblemsinvolvingthevectorproduct,
Y
=
K
,
1
X
k
=0
A
k
X
k
1 where
X
isanunknownvector,butthevector
A
isknownatcompiletime.Althoughwedevelopa methodologybasedonthissimplevectorproduct,the sametechniquesareapplicabletoanymultiplecon- stantmultiplicationproblem. Webeginbydecomposingthevectorproductina mannerthattakesadvantageofour
apriori
knowledge oftheconstantvector
A
.Specically,wewrite
A
k
=
L
,
1
X
l
=0
a
lk
2
l
;
where
a
lk
isasinglebitand
L
istheprecisionofthe coecients.Weassumeforsimplicitythat
A
k
isa positiveinteger,butthederivationcanbeappliedto signedxed-pointsystemsaswell.Substitutingthis into1gives
Y
=
K
,
1
X
k
=0
X
k
L
,
1
X
l
=0
a
lk
2
l
!
;
andafterexchangingtheorderofsummations,we have
Y
=
L
,
1
X
l
=0
K
,
1
X
k
=0
X
k
a
lk
!
2
l
:
2 Notethat
a
L
,
1
;
k
denotesthemostsignicantbitof thecoecient
A
k
. Therearesomeimportantfeaturesof2that shouldbenoted.First,nohardwaremultipliersare needed,since
a
lk
takesonvalues0or1,leavingonly shiftstoimplementthe2
l
multiplication.Second, thedecompositionof
A
intobit-planesbyequation 2allowsforsimpleexploitationofthesymmetries andcommonsubexpressionscontainedinthecoe- cientdata.Moreover,since
a
lk
isknownatcompile time,weperformonlytheadditionsthatarenecessary duringruntime. Inordertogeneratetreesfromavectorproduct,it isusefultorepresent2inthefollowingmanner:
2 4
Y
0
Y
1
::: Y
L
,
1
3 5
=
2 4
a
0
;
0
a
0
;
1
:::a
0
;K
,
1
a
1
;
0
::: :::::: a
L
,
1
;
0
a
L
,
1
;K
,
1
3 5 2 4
X
0
X
1
::: X
K
,
1
3 5
;
withthedesiredresult
Y
=
Y
0
+
Y
1
2
1
+
:::
+
Y
L
,
1
2
L
,
1
:
Denotethecoecientmatrixof
a
lk
elementsforout- put
Y
as
a
Y
.Thismatrixwillbethebasisofallop- timizationsandtransformationsinthispaper.Note that
a
Y
consistsofbinarydataonly,withthetoprow containingtheleastsignicantbitsofthe
K
elements of
A
,andthebottomrowcontainingtheirmostsig- nicantbits. Theproductofeachrowof
a
Y
with
X
iscomputed usingabinarytree;ifarowof
a
Y
containsoneormore 0's,thenthecorrespondingtreewillbeaprunedtree. Regardless,the
L
treesY
0
,Y
1
,...Y
L
,
1
aresummedto- getherusingonenaladdertreecombinedwithshifts toproducethevalueof
Y
.Forsimplicity,ourgures showalinearizedversionofthisnaltree;inpractice abinarytreewilloftenbeused3. Asanexampleusedthroughoutthissection,sup- posewewishtocompute
Y
=
X
0
+2
X
1
+3
X
2
+4
X
3
+5
X
4
+6
X
5
+7
X
6
+8
X
7
:
Inthiscase
A
=12345678,and
a
Y
is
2 6 4
10101010 01100110 00011110 00000001
3 7 5
:
3
+++ + + +++
+
+
++
Figure1:Anunoptimizedaddertreeforcomputing avectorproduct.Shadedregionsrepresent1'sina coecient'sbitplane. Figure1illustratestheunoptimizedtreestructureto computethisexpressionforanarbitraryvector
X
.The coecientsforthefoursubtreesfromlefttorightcor- respondtotherowsof3fromtoptobottom. TheleavesofFigure1areregisterstoholdthevec- tor
X
;asillustratedtherearefourcopiesof
X
,one foreachbitplaneofcoecientdata.Thetreeiscon- structedsuchthattheshift-addsoccurinorderofsig- nicance:recallthatthedata'smostsignicantbits, inourrepresentation,arelocatedatthebottomrow of
a
Y
.Thisrowisshiftedleftonebitandaddedto thenextrowaboveit,withtheprocessrepeatingfor eachrow.Thus,Figure1computes
Y
=
X
0
+
X
2
+
X
4
+
X
6
+ 2
X
1
+
X
2
+
X
5
+
X
6
+ 2
X
3
+
X
4
+
X
5
+
X
6
+2
X
7
:
Notethatthetreeiscompletelyspeciedbythe datacontainedin
a
Y
;thisallowsustooptimizethe treestructuresimplybyapplyingtransformationsto thematrix
a
Y
.
4Optimizations
MCMTsrelyheavilyoncommonsubexpression eliminationCSEtooptimizetheaddertrees.CSE isimplementedeasilyintrees,sinceacommonsubex- pressionisasubtreecommontotwoormoredier- enttrees,andiseliminated"bysharingonesubtree's outputandremovingtheothers.Whilenon-trivial forrandomlogic,theformulationof
a
Y
allowsforthe following,systematicapproach.
4.1Sharingcommonsubexpressions
SincethefoursetsofeightleavesinFigure1contain identicalvalues,ahardwarevectormultiplierwould combinethefoursubtreescorrespondingtoY
0
,Y
1
, Y
2
,andY
3
intoasingletree.Acloseinspectionof Figure1revealsredundanciesinthesubtrees,suchas thevertexconnectedtoX
5
andX
6
inbothY
1
and Y
2
;clearly,onlyoneadderisnecessary,andthuswe labelX
5
+X
6
asacommonsubexpression.Thiscan beseeninthematrix
a
Y
inFigure2,withthefour 1'smarked
2
.Sinceaddersareusedtocomputeeach row,whenevertwoormore1'smatch,thereisapos- sibilityofacommonsubexpression. Ingeneral,asubexpression
isasetoflocationsof 1'sin
a
Y
,wheretherowandcolumnsizeisatleasttwo sinceanadderneedsatleasttwooperands.Aformal denitionofsubexpressionsisnowprovided,conclud- ingwiththedenitionofa
valid
groupofsubexpres- sions. Denethe
dotproduct
oftwosets
A
and
B
as
A
B
=
f
a;b
:
a
2
Aandb
2
B
g
:
Giventhat
a
Y
isofsize
L
K
,dene
C
tobetheset ofcolumnsof
a
Y
,
C
=
f
0
;
1
;:::;K
,
1
g
;
and
R
tobethesetofrowsof
a
Y
,
R
=
f
0
;
1
;:::;L
,
1
g
:
Giventhat2
R
and2
C
arerespectivelythe
powersets
of
R
and
C
,the
i
-thcommonsubexpression
i
of
a
Y
isdenedas
i
=
R
i
C
i
;
where
R
i
and
C
i
aresets thatmeetthefollowingconditions: 1.
R
i
2
2
R
and
C
i
2
2
C
2.
a
r;c
a
r
0
;c
0
=1forall
r;r
0
2
R
i
and
c;c
0
2
C
i
3.
j
R
i
j
2and
j
C
i
j
2 InFigure2,forexample,
R
1
=
f
0,1
g
and
C
1
=
f
2,6
g
. TwoexampleCSEsareillustratedinFigure2. Both
1
and
2
containfourelements,and
j
R
j
=
j
C
j
= 2forbothaswell.Notealsothat
1
T
2
=
f
1
;
6
g
. Ingeneral,intersecting
'sproducevalidcircuits,but inthiscaseitdoesnotsince
a
1
;
6
wouldbeadded twice.Thus,wemustalterthedenitionofinter- sectionslightlyinordertoguaranteeacorrectresult.
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