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Table Of Contents

Tutorial Contents
Tutorial Flows
•HDL Design Flow
•Schematic Design Flow
HDL Design Flow
Schematic Design Flow
Implementation-only Flow
Additional Resources R
Additional Resources
Overview of ISE and Synthesis Tools
•“Overview of ISE”
Overview of ISE
Project Navigator Interface
Sources Window
Sources Tab
Snapshots Tab
Libraries Tab
Processes Window
Processes Tab
Transcript Window
Error Navigation to Source
Error Navigation to Answer Record
Using Revision Control Features R
Design Summary
Text Editor
ISE Simulator / Waveform Editor
Schematic Editor
Using Revision Control Features
Using Snapshots
Creating a Snapshot
Restoring a Snapshot
Viewing a Snapshot
Using Project Archives
Creating an Archive
Restoring an Archive
Using Export/Import Source Control
Exporting a Project
To export a project
Xilinx Synthesis Technology (XST)
HDL-Based Design
•“Overview of HDL-Based Design”
Overview of HDL-Based Design
Getting Started
Required Software
Optional Software Requirements
VHDL or Verilog?
Installing the Tutorial Project Files
Starting the ISE Software
Creating a New Project
Creating a New Project: Using the New Project Wizard
Creating a New Project: Using a Tcl Script
Stopping the Tutorial
Design Description
Functional Blocks
Design Entry
Adding Source Files
Checking the Syntax
Correcting HDL Errors
Creating an HDL-Based Module
Using the New Source Wizard and ISE Text Editor
Using the Language Templates
Adding a Language Template to Your File
Creating a CORE Generator Module
To create a CORE Generator module:
Instantiating the CORE Generator Module in the HDL Code
Creating a DCM Module
Using the Clocking Wizard
Instantiating the dcm1 Macro - VHDL Design
Instantiating the dcm1 Macro - Verilog
Synthesizing the Design
•“Synthesizing the Design using XST”
Synthesizing the Design using XST
Entering Constraints
Entering Synthesis Options
To enter synthesis options:
The RTL / Technology Viewer
Synthesizing the Design using Synplify/Synplify Pro
Examining Synthesis Results
Resource Utilization
Synthesizing the Design Using Precision Synthesis
Overview of Schematic-Based Design
Creating a New Project: Using New Project Wizard
Opening the Schematic File in the Xilinx Schematic Editor
Manipulating the Window View
Creating a Schematic-Based Macro
Defining the time_cnt Schematic
Adding I/O Markers
Adding Schematic Components
Adding Buses
Adding Bus Taps
Adding Net Names
Checking the Schematic
Saving the Schematic
Creating and Placing the time_cnt Symbol
Creating the time_cnt symbol
Placing the time_cnt Symbol
Creating a State Machine Module
Adding New States
Adding a Transition
Adding a State Action
Adding a State Machine Reset Condition
Creating the State Machine HDL output file
Creating the State Machine Symbol
Creating the dcm1 Symbol
Creating the debounce Symbol
Placing the statmach, timer_preset, dcm1 and debounce Symbols
Changing Instance Names
Hierarchy Push/Pop
Specifying Device Inputs/Outputs
Adding Input Pins
Adding I/O Markers and Net Names
Assigning Pin Locations
Completing the Schematic
Behavioral Simulation
•“Overview of Behavioral Simulation Flow”
•“ModelSim Setup”
Overview of Behavioral Simulation Flow
ModelSim Setup
ModelSim PE and SE
ModelSim Xilinx Edition
ISE Simulator Setup
Required Files
Design Files (VHDL, Verilog, or Schematic)
Test Bench File
Xilinx Simulation Libraries
Updating the Xilinx Simulation Libraries
Mapping Simulation Libraries in the Modelsim.ini File
Adding an HDL Test Bench
Adding Tutorial Test Bench File
VHDL Simulation
Verilog Simulation
Behavioral Simulation Using ModelSim
Locating the Simulation Processes
Specifying Simulation Properties
Performing Simulation
Adding Signals
Adding Dividers
Analyzing the Signals
Saving the Simulation
Behavioral Simulation Using ISE Simulator
Rerunning Simulation
Creating a Test Bench Waveform Using the Waveform Editor
Creating a Test Bench Waveform Source
Applying Stimulus
Chapter 5
Design Implementation
•“Overview of Design Implementation”
Overview of Design Implementation
Continuing from Design Entry
Starting from Design Implementation
Specifying Options R
Specifying Options
Creating Partitions R
Creating Partitions
Creating Timing Constraints
Translating the Design R
Translating the Design
Using the Constraints Editor
Using the Floorplan Editor
Mapping the Design
Using Timing Analysis to Evaluate Block Delays After Mapping
Estimating Timing Goals with the 50/50 Rule
Report Paths in Timing Constraints Option
Placing and Routing the Design R
Placing and Routing the Design
Using FPGA Editor to Verify the Place and Route R
Using FPGA Editor to Verify the Place and Route
Evaluating Post-Layout Timing R
Evaluating Post-Layout Timing
Changing HDL with Partition
Creating Configuration Data
Creating a PROM File with iMPACT
Command Line Implementation
Timing Simulation
•“Overview of Timing Simulation Flow”
Overview of Timing Simulation Flow
Specifying a Simulator
Timing Simulation Using ModelSim
Specifying Simulation Process Properties
Timing Simulation Using Xilinx ISE Simulator
Viewing Full Signal Names
iMPACT Tutorial
•“Device Support”
Device Support
Download Cable Support
Parallel Cable IV
Platform Cable USB
MultiPRO Cable
Configuration Mode Support
Generating the Configuration Files
Connecting the Cable
Starting the Software
Opening iMPACT from Project Navigator
Opening iMPACT stand-alone
Creating a iMPACT New Project File
Using Boundary Scan Configuration Mode
Specifying Boundary Scan Configuration Mode
Assigning Configuration Files
Saving the Project File
Editing Preferences
Performing Boundary Scan Operations
Verifying Chain Setup
Creating an SVF File
Setting up Boundary Scan Chain
JTAG chain setup for SVF generation
Manual JTAG chain setup for SVF generation
Writing to the SVF File
Stop Writing to the SVF
Playing back the SVF or XSVF file
Other Configuration Modes
Slave Serial Configuration Mode
SelectMAP Configuration Mode
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Xilinx Tut

Xilinx Tut

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Published by Ashish Pandey

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Published by: Ashish Pandey on Nov 12, 2010
Copyright:Attribution Non-commercial


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