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Table Of Contents

1.2 The frontend in TV broadcasting
Figure 1.2 Heterodyne Receiver _ Terrestrial TV Frontend
Figure 1.3 DVB Satellite transmission modes
Figure 1.5 Local Oscillator Spectral Purity X SNR
1.3 Current tendencies: low noise and higher integration
Figure 1.6 Carrier Spectrum
Figure 1.8 Phase Noise requirements
1.4 PLL systems : different application contexts
1.5 PLL frequency synthesizers constituting blocks and nomenclature
Figure 1.9 PLL frequency synthesizer: block diagram
Figure 1.10 VCO and tunable resonator
1.5.2 Dividers
1.5.3 Phase Detector – Charge Pump
Figure 1.11 Phase Detector & Charge Pump block diagram
Figure 1.12 Phase detector & Charge pump: transfer and state machine
1.5.4 Loop Filter
2. PLL Phase Model and Loop Filter calculation 21
2 PLL Phase Model and Loop Filter calculation
2.1 Phase Model for PLL synthesizers
2.1.1 Requirements in the Time and Frequency Domain
Figure 2.2 Vtune time response for a frequency step
Figure 2.3 Locked VCO output spectrum
2.1.2 Second-Order Loop
2.1.3 Third and Fourth Order Loops
Figure 2.7 Gain Variation X Stability in Bode Plots
2.2 Algorithm for the Loop Filter Calculation
2.2.1 Nominal Design
Figure 2.8 The influence of r21 in the gain-bandwidth variation
order filter: Phase Margin Variation for wol ∈ [ wz1 , wp2 ]
2.2.3 Summary of steps and numerical example
Figure 2.9 Numerical example of robust filter design
3. Application Related Constraints 43
3 Application Related Constraints
3.1 Reference Breakthrough
3.2 VCO Noise Representation and Phase Noise Units
Figure 3.2 Free running VCO power spectrum density
3.3 Optimum Closed Loop Bandwidth
Figure 3.5 Combined Spectrum: PLL + VCO noise contributions
3.4 PLL Closed Loop Bandwidth
3.4.1 w3dB derivation from BRL(s)
Table 3-1 Comparing the denominators of B(s) and BRL(s)
3.4.2 w3dB derivation from was
3.5 Maximum Phase Jitter
Figure 3.8 Optimizing Total Phase Deviation
Figure 3.9 Maximum SSB noise requirement
3.6 Gain Stability Boundary
4. Active Loop Filters: AC & disturbances issues 69
4 Active Loop Filters: AC & disturbances issues
4.1 Non-ideal Filter Impedance
Figure 4.1 Active Loop Filter
4.1.2 Amplifier AC characteristics
Figure 4.3 Active Filter AC model
Figure 4.4 Loop rootlocus with active filter
4.1.4 Numerical example
Table 4-2 Active Filter example: Phase Margin degradation
4.1.5 Input impedance: Zin
4.1.6 Summary of AC boundaries for filter design
4.2 Disturbances and Noise Propagation
4.2.1 Random Electrical Noise
4.2.2 Supply Disturbances
Figure 4.7 Supply disturbances
4.2.3 Amplifier Noise
Figure 4.8 Amplifier noise
4.2.4 Filter Component Noises
Figure 4.9 Filter components noise
4.2.5 Transfer functions table
Table 4-3 Disturbances transfer functions
4.2.6 Simulation Example
Figure 4.11 Noise simulation results
5. Limitations of the LTI Phase Model 89
5 Limitations of the LTI Phase Model
5.1 Three-state comparator: frequency and phase detector
Figure 5.1 Phase-detector & Charge Pump transfer
5.1.1 Minimum phase deviation range
Figure 5.3 Condition for unlimited frequency tracking range
5.2 DC range limitations
5.2.1 Loop filter time domain response
Figure 5.5 Time response through normalized functions
5.2.2 Numerical examples and design considerations
5.3 Lock convergence approaches
5.3.2 Phase approach
Figure 5.8 Phase approach convergence criterion
Figure 5.11 Convergence approaches X gain variation
5.4 Discrete transfers for the PLL Phase Model
5.4.1 The sampler
5.4.2 The holder
Figure 5.14 Charge Pump DAC output
5.4.3 Continuous equivalent with transmission delay
Figure 5.15 Continuous equivalent with transmission delay
Figure 5.16 Frequency and Time response for the continuous + delay model
6. Phase Noise: theoretical to practical approach 119
6 Phase Noise: theoretical to practical approach
6.1 Electrical Noise: random source representation & measurements
6.1.1 Electrical noise as a random process
6.1.2 Measuring Phase Noise
Figure 6.1 Spectrum Analyzer Output
6.2 Phase Noise Notations
6.2.1 Interchanging Modulation Types
Table 6-1 Phase Modulated Carrier
6.2.1.1 Angular modulation
Figure 6.2 FM & PM carriers
Figure 6.3 SSB superposed noise: AM + PM decomposition (phasor)
Figure 6.4 Superposed Noise: AM + PM decomposition (spectrum)
Figure 6.6 Phase deviation from DSB sidebands
6.2.3 Slope approach
Figure 6.7 Slope approach: voltage & time deviations
6.3 Large Signal Linearization
6.3.1 Time and Frequency representation
Figure 6.8 Periodic transfer determined by a large signal
6.3.2 Linear Time Variable transfer
7. Phase Noise in the PLL context 141
7 Phase Noise in the PLL context
Figure 7.1 PLL block diagram with signal+noise inputs
Figure 7.2 Noise Transfer Slopes
7.1 Translating the SNF into phase, time, voltage and current noise
Figure 7.3 Synthesizer Noise Floor
Table 7-1 Data sheet points from: TSA5059 - low noise PLL
7.2 Sampling effects: SNF x fcp
Figure 7.4 Sampled Loop Model
7.2.1 Narrow bandwidth noise sources
Table 7-2 The influence of fcp change for narrow band noise
7.2.2 Large bandwidth noise sources
Figure 7.5 Large bandwidth noise folding
Table 7-3 The influence of fcp change for large band noise
7.3 Detailing noise sources in different PLL blocks
7.3.1 D-flip flop
Figure 7.6 DFF plus superposed noise in the clock input: time domain signals
7.3.2 Charge Pump
Figure 7.8 Charge Pump current noise levels within one period
7.4 Behavioural Models
7.4.1 Frequency domain
Figure 7.9 Behavioural model of the PLL for AC and noise simulations
7.4.2 Time domain
Figure 7.10 Behavioural model of the PLL for transient simulations
7.5 Implementation Loss due to Phase Deviations
Figure 7.11 Digital Demodulator and Decoder
7.5.1 Signal to noise ratio and implementation loss
Figure 7.13 Behavioural Model of the Carrier Recovery loop
8 Testchips Realized
8.1 Gm-C oscillator
Figure 8.1 Gm-C integrated oscillator
8.1.2 Results
Table 8-1 Measurements of the frequency coverage of the QCCO
8.2 TC2 : Mixer-Oscillator-PLL circuit for satellite direct conversion
8.2.1 Double Loop Synthesizer
Figure 8.2 Double loop MOPLL: block diagram
Table 8-2 Double Loop: minimum step and comparison frequencies
Figure 8.3 Block diagram of TC2
Figure 8.4 Photo of a testchip TC2
8.2.3 TC2: results
Figure 8.5 TC2 _ in-loop spectrum for N1=7 and fcp1=300Mhz
8.3 TC3 : single PLL plus QCCO circuit
Figure 8.7 TC3 _ single low noise PLL plus QCCO
Figure 8.8 Simulation result for the SSB phase noise _ linear scale
8.4 Comparative analysis: phase jitter and implementation loss
8.4.1 Configurations compared
8.4.2 Conditions for the simulations
Table 8-4 Parameters and outputs for comparative analysis
Table 8-5 Settings of the demodulator block
Figure 8.9 Spectra for ∆fstep =125kHz and flo =900MHz
8.4.3 Results and conclusions
Table 8-6 Phase Jitter and implementation loss for rs=30Msps and fLO = 2,2GHz
Table 8-7 Phase Jitter and implementation loss for rs=3Msps and ∆fstep = 125kHz
Table 8-8 Margin for degradations in the oscillators phase noise performance
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PLL Frequency Synthesizers, Phase Noise and Wide Band

PLL Frequency Synthesizers, Phase Noise and Wide Band

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Published by: Jeff on Nov 14, 2010
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11/27/2012

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