Instituto Tecnológico de Chihuahua ELECTRO 2001

A NOVEL CMOS CHARGE-PUMP CIRCUIT WITH POSITIVE FEEDBACK FOR

PLL APPLICATIONS

Esdras Juárez-Hernández and Alejandro Díaz-Sánchez

Instituto Nacional de Astrofísica, Optica y Electrónica
Luis Enrique Erro #1 Sta. Ma. Tonantzintla. Puebla-México.

Instituto Tecnológico de Puebla

Avenida Tecnológico número 420, Colonia Maravillas, Puebla, Pue.
E-mail: esdrasj@susu.inaoep.mx, adiazsan@inaoep.mx

ABSTRACT: The design and simulation of a
novel CMOS charge-pump topology for RF
frequency synthesizers is presented. Based on
positive feedback and current reuse, the switching
speed is increased and the power consumption is
reduced. Simulation results, shows that the
structure is suited for low-voltage and high
frequency applications.
1. INTRODUCTION
In recent years, the fast growth of cellular
communications systems has motivated an
DWN are low (third state), the net current is zero
and Vo remains constant.
The traditional charge pumps circuits make use of
the excellent properties that MOS switches have.
However, if they are used to directly replace the
ideal switches of fig.1, a voltage error component is
generated due to charge injection and
clockfeedthrough. These errors cause a jump in the
stored voltage on CL that is transformed in phase
noise and spurs in the VCO [3].
VDD

increasing demand of high performance integrated

IB
RF components [1]. One of the most important
blocks of these systems, is the local oscillator (LO).
The need of a well defined and highly stable signal A
UP
Vo
for the local oscillator, make necessary the use of PFD
B
phase locked loop techniques to satisfy the DWN CL

stringent requirements of standards like GSM [2].

Among the different PLL topologies, the PLL IB
charge pump is widely used because of the
advantages offered versus the traditional XOR/LPF VSS
approach [3]. A fundamental block is the charge Figure 1. Conceptual representation of the Charge-
pump, since this circuit controls the VCO Pump circuit.
frequency. Phase-noise is the most critical
parameter in the VCO. Reduction of this can be VDD

realized increasing the PLL loop-bandwidth.

However, increase the loop-bandwidth requires a IB

high-speed charge-pump.
A UP
2. TRADITIONAL CHARGE-PUMP CIRCUITS PFD
Vo

Figure 1, show the concept of a charge pump B

DWN CL

circuit. It consists in two switched current sources

driving a capacitor. Switching is realized by means
IB
of a three-state phase-frequency detector (PFD).
When UP signal is high and DWN is low (first VSS
state), I1 deposits charge onto C, rising Vo. On the
Figure 2. Charge injection and clock-feedthrough
other hand, when UP is low and DWN is high errors in MOS switches.
(second state), I2 sink current and the output
voltage is decreased. Finally, when both UP and

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3. PROPOSED ARCHITECTURE consumption is generated. These three parameters

Since the problems discussed in the previous
section, some topologies have been proposed in
order to improve this. Current steering techniques
are widely used because this allows obtain fast
switching and low charge injection errors [4,5].
Figure 3 shows the basic circuit proposed by Chang
et al.
VDD
trade each with the other to satisfy the required
performance. The proposed topology makes use of
the current source IB when it is steered through
M1, charging the node A and thus reducing the
power consumption (fig. 4). Since the current
injection is greater than the previous structure, M4
is turned-off faster.
VDD

M5 M6
M5 M6

VDD B
IS
VDD

M3 M4
M3 M4
Iout
VDD A Iout
A
UP UP
M1 M2 UP UP
M1 M2

IB
IB

VSS
Figure 3. Basic circuit proposed by Chang et al.
It consists in a current switch (M1-M2) with a
current mirror load (M3-M4) and a pull-up current
mirror (M5-M6). The current switch is driven by
the differential signals provided by the PFD. Thus,
when the signal UP+ is greater than UP-, the
current source IB is steered on M2. The current
difference between Is and IB is mirrored by M3 and
M4, producing the charge/discharge current. On the
other hand, when Up+ is lower than UP-, IB is
steered on M1. The pull-up circuit is used to
increase the charge speed of the node A. If the pull-
up circuit is not used, when the current of the input
pair is steered through M1, M3 still conducts for a
few time. This produces a temporal current, which
introduce spurs and phase-noise at the VCO output.
The time constant associated with this node is not a
well-controlled parameter, but more important,
constitute a slow path. The complete configuration
makes use of two identical circuits and a wide
swing current mirror. Although the improved
performance, this circuit still presents several
drawbacks. When the current source IB is steered
through M1, this current is wasted since it is not
any more utilized. In same way, the current Is must
be enough small to no increase the power
consumption. Furthermore, since this current only
operates for a given time, unavoidable static power
VSS
Figure 4. Modification for current reuse.
However, the problem of the slow path still
continues, since we have only translated the
problem to the other branch. To solve this, another
transistor (M7) is added. The final configuration is
a simple positive feedback amplifier with gain
enhancement [5], where the switching speed is
increased. Figures 3 to 5, shows the evolution of
the topology and figure 6, the complete circuit used
in this work. The amount of positive feedback and
gain are given by:
α = (W / L )5 (W / L )6
(1)
µn(W / L )1 1
Av =
µp(W / L )2 1 − α
where: (W/L)1=(W/L)2, (W/L)3=(W/L)6 and
(W/L)3=(W/L)5
The switching speed depends of IB and of the stray
capacitance associated to node A. The capacitance
in the node A is given by:
C A ≈ CGS3 + CGS4 + CGS7 + CDB2 + CDB5 + CDB7 (2)

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Instituto Tecnológico de Chihuahua ELECTRO 2001

VDD
4. SIMULATION RESULTS
M3 In order to show the capabilities of the circuit,
M5 M6 M7 M4
simulations in H-SPICE have been realized for a
Iout 0.35 µm CMOS technology with BSIM3V3
B A Level=49 model parameters. These results are
UP UP shown in figures 7 and 8. In this work, we have
M2
M1
employed a simple current mirror for the 1:1
current converter, but the idea can be extended to
other topologies (like a low-voltage cascode current
IB mirror), depending of the requirements that must be
satisfied.
VSS

Figure 5. Final basic topology with positive

feedback for increases the switching speed.

VDD

M6 M7 M7 M6
M3 M4 M5 M5 M4 M3

Vo
B A A B

DWN DWN CL UP UP
M1 M2 M2 M1

1:1

IB IB

VSS VSS
Figure 7. Pumping-up of the proposed charge-
Figure 6. Circuit used in this work. pump.

From equation (1), we obtain that the maximum

value for α must be 1 or the hysteresis phenomenon
occurs. A practical value for this parameter is 0.75
[7].

The switching point of the input differential

amplifier is given by:

4 IB
V SW = 2 (VGS1 − VT 1 ) = (3)
Kn(W L )1

In this way, a trade-off between switching point

and capacitance must be realized. In the present Figure 8. Pumping-down of the proposed charge
pump circuit.
work, that design requirement is relaxed by using
rail-to-rail input signals.

Furthermore, for low-voltage operation VDD must The frequency of operation is 100 MHZ with
be satisfy: VDD=2V. Differential signals of PFD are
generated by a Shoji’s delay balanced chain [8].
Figure 9, shows the output current during pumping-
VDD ≥ VD SATB + 2VDS SAT 1 + VTP (4)
down phase and figures 10 and 11 show the
transient response of the node A for a VDD=3V
Therefore, for typical design values, VDD can be version. From these, it can be seen that positive
as low as 1.5V. However, in order to maintain M1 feedback and current reuse allows obtain a faster
in saturation, input signals must be lower than switching speed.
VDD, requiring special generation.

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Instituto Tecnológico de Chihuahua
Figure 9. Output current in the pumping-down
phase (f=100 MHz, VDD=2V).
Figure 10. Transient response of the Chang circuit.
Figure 11. Transient response of the node A for
the proposed circuit (VDD=3V)
5. CONCLUSIONS
A novel CMOS charge-pump circuit has been
presented. Positive feedback and current reuse
allows obtain a faster switching speed and low
power consumption respectively, shown a better
performance that previously reported structures.
Simulations show that the circuit is capable of
operate at low voltage without degrading speed,
making this structure suitable for low-voltage &
wide-band RF PLL applications.
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ELECTRO 2001
6. REFERENCES
[1] J. L. Finol and David Lovelace, “Building
Blocks for Digital Wireless Communications
in Sub-Micron Technologies: An Overview”.
Motorola Semiconductor Products.
[2] ETSI, “Digital cellular telecommunications
system (Phase 2+); Radio transmission and
reception (GSM 5.05)”, European
Telecommunications Standards Institute,
Copyright 1996.
[3] Behzad Razavi. RF Microelectronics.
Prentice-Hall. Upper Saddle River. NJ. 1998.
[4] R. C. Chang and L. C. Kuo, “A new Low-
Voltage Charge Pump Circuit for PLL”, IEEE
International Symposium of Circuits and
Systems ISCAS, Switzerland, May 2-5, 2000,
pp. 701-703.
[5] J. F. Parker and Daniel Ray, “A 1.6 GHZ
CMOS PLL with on Chip Loop Filter” IEEE
Journal of Solid State Circuits, vol. 33, No. 3,
March 1998, pp. 337-343.
[6] R. Wang and R. Harjani, “Partial Positive
Feedback for Gain Enhancement of Low
Power OTA’s”. Analog Integrated Circuits
and Signal Proc. Vol. 8. Kluwer Academic,
1995, pp. 20-35.
[7] R. Gregorian, Introduction to MOS Op-Amps
and Comparators, John Wiley and Sons. 1999.
[8] M. Shoji, “Elimination of process dependent
clock skew in CMOS VLSI”. IEEE Journal of
Solid State Circuits, vol. sc 21, no. 5. October
1986.