DESIGN OF INTELLIGENT TLC BASED ON VHDL

1.1 INTRODUCTION:

Traffic light controller establishes a set of rules and instructions that drivers, pilots, train
engineers, and ship captains rely on to avoid collisions and other hazards. Traffic control systems
include signs, lights and other devices that communicate specific directions, warnings, or
requirements.

They are already mentioned that MCU, PLC and so on can be used as the hardware of
traffic light controller. There are several control ways, such as neural networks, fuzzy control
and etc. However, only the research and implementation of 2-phase traffic light controller was
mentioned in the cited references above. While in actual application, multi-branch intersections
and the case that it has obvious change of traffic flow in the same intersection on different time
are commonly exist. Therefore, adjustable multi-phase intelligent traffic light controller is
needed. The adaptability and applicability of the system can be strengthened if the specific phase
of the traffic light controller can be chosen by the number of the intersection branches and the
traffic flow. So, according to the above analysis, this paper provides the design thought of
adjustable multi-phase traffic light controller based on VHDL language, and give the right
simulation results by using XILINX.

Fast transportation systems and rapid transit systems are nerves of economic
developments for any nation. All developed nations have a well developed transportation system
with efficient traffic control on road, rail and air. Transportation of goods, industrial products,
manpower and machinery are the key factors which influence the industrial development of any
country. Mismanagement and traffic congestion results in long waiting times, loss of fuel and
money. It is therefore utmost necessary to have a fast, economical and efficient traffic control
system for national development.

The monitoring and control of city traffic is becoming a major problem in many
countries. With the ever increasing number of vehicles on the road, the Traffic Monitoring
Authority has to find new methods of overcoming such a problem. The measures taken are
development of new roads and flyovers in the middle of the city; building of several ring such as

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the inner ring road, middle ring road and outer ring road; introduction of city trains such as the
light rapid transit (LRT), and monorails; restricting of large vehicles in the city during peak
hours; and also development of sophisticated traffic monitoring and control systems. Growing
numbers of road users and the limited resources provided by current infrastructures lead to ever
increasing traveling times.

One way to improve traffic flow and safety of the current transportation system is to
apply automation and intelligent control methods to roadside infrastructure and vehicles.
Transportation research has the goal to optimize transportation flow of people and goods. As the
number of road users constantly increases, and resources provided by current infrastructures are
limited, intelligent control of traffic will become a very important issue in the future.

The problems of typical conventional traffic light Controller are mentioned below:

1.1.1 Heavy Traffic Jams

With increasing number of vehicles on road, heavy traffic congestion has substantially increased
in major cities. This happened usually at the main junctions commonly in the morning, before
office hour and in the evening, after office hours. The main effect of this matter is increased time
wasting of the people on the road. The solution for this problem is by developing the program
which different setting delays for different junctions. The delay for junctions that have high
volume of traffic should be setting longer than the delay for the junction that has low of traffic.
This operation is calling Normal Mode.

1.1.2 No traffic, but still need to wait

At certain junctions, sometimes even if there is no traffic, people have to wait. Because the
traffic light remains red for the preset time period, the road users should wait until the light turn
to green. If they run the red light, they have to pay fine. The solution of this problem is by
developing a system which detects traffic flow on each road and set timings of signals
accordingly. Moreover, synchronization of traffic signals in adjacent junctions is also necessary.

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1.1.3 Emergency car stuck in traffic jam

Usually, during traffic jam, the emergency vehicle, such as ambulance, fire brigade and police
will be stuck especially at the traffic light junction. This is because the road users waiting for the
traffic light turn to green. This is very critical problem because it can cause the emergency case
become complicated and involving life.

1.1.4 Lack of Traffic Information to users

Present traffic systems fail to provide traffic information including congested roads and alternate
routes available in case of congestion.

In the proposed Intelligent Traffic Light Controller (ITLC) all these limitations of
existing controller are eliminated. The proposed project of ‘Intelligent Traffic Light Controller’
uses based on VHDL and has advantages of efficient control and fast response time. The
problem of fixed timing traffic light is totally eliminated in this project.

Most of the present intelligent traffic lights are sensor based with a certain algorithm that
controls the switching operation of the system. This approach considers the traffic to be moving
smoothly and hence does not require any management or monitoring of traffic conditions.

1.2 BACKGROUND:

Traffic light optimization is a complex problem. Even for single junctions there might be
no obvious optimal solution. With multiple junctions, the problem becomes even more complex,
as the state of one light influences the flow of traffic towards many other lights. Another
complication is the fact that flow of traffic constantly changes, depending on the time of day, the
day of the week, and the time of year. Roadwork and accidents further influence complexity and
performance.

In practice most traffic lights are controlled by fixed-cycle controllers. A cycle of

configurations is defined in which all traffic gets a green light at some point. The split time
determines for how long the lights should stay in each state. Busy roads can get preference by

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adjusting the split time. The cycle time is the duration of a complete cycle. In crowded traffic,
longer cycles lead to better performance. The offset of a cycle defines the starting time of a cycle
relative to other traffic lights. Offset can be adjusted to let several lights cooperate, and for
example create green waves.

Fixed controllers have to be adapted to the specific situation to perform well. Often a
table of time-specific settings is used to enable a light to adapt to recurring events like rush hour
traffic. Setting the control parameters for fixed controllers is a lot of work, and controllers have
to be updated regularly due to changes in traffic situation. Unique events cannot be handled well,
since they require a lot of manual changes to the system. Fixed controllers could respond to
arriving traffic by starting a cycle only when traffic is present, but such vehicle actuated
controllers still require lots of fine-tuning.

Most research in traffic light control focuses on adapting the duration or the order of the
control cycle. In our approach we do not use cycles, but let the decision depend on the actual
traffic situation around a junction, which can lead to much more accurate control. Of course, our
approach requests that Information about the actual traffic situation can be obtained by using
different sensors or communication systems.

1.3 WHY VHDL:

1.3.1 INTRODUCTION TO VHDL:

 The VHSIC Hardware Description Language (VHDL) is any industry standard language
used to describe hardware from the abstract to concrete level.
 The language not only defines the syntax but also defines very clear simulation
semantics for each language construct.
 It is strong typed language and is often verbose to write.
 Provides extensive range of modeling capabilities, it is possible to quickly assimilate a
core subset of the language that is both easy and simple to understand without learning
the more complex features.

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Very Large Scale Integration

– design/manufacturing of extremely small, complex circuitry using modified

semiconductor material
– integrated circuit (IC) may contain millions of transistors, each a few mm in size
– applications wide ranging: most electronic logic devices

1.3.2 ORIGINS OF VHDL:

Much development motivated by WWII need for improved electronics, especially for radar

 1940 - Russell Ohl (Bell Laboratories) - first pn junction

 1948 - Shockley, Bardeen, Brattain (Bell Laboratories) - first transistor 1956 Nobel
Physics Prize
 Late 1950s - purification of Si advances to acceptable levels for use in electronics
 1958 - Seymour Cray (Control Data Corporation) - first transistorized computer - CDC
1604
 1959 - Jack St. Claire Kilby (Texas Instruments) - first integrated circuit - 10 components
on 9 mm2
 1959 - Robert Norton Noyce (founder, Fairchild Semiconductor) - improved integrated
circuit
 1968 - Noyce, Gordon E. Moore found Intel
 1971 - Ted Hoff (Intel) - first microprocessor (4004) - 2300 transistors on 9 mm2
 Since then - continued improvement in technology has allowed for increased
performance as predicted by Moore’s Law

1.3.3 WHY USE VHDL?

 Quick Time-to-Market
o Allows designers to quickly develop designs requiring tens of thousands of logic
gates
o Provides powerful high-level constructs for describing complex logic
o Supports modular design methodology and multiple levels of hierarchy

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 One language for design and simulation

 Allows creation of device-independent designs that are portable to
 Multiple vendors. Good for ASIC Migration
 Allows user to pick any synthesis tool, vendor, or device
 A very verbose, complex, and powerful language for design, simulation, verification and
synthesis of digital systems
 Supports many levels of abstraction, ranging from algorithm level to gate level
 Can model concurrent and sequential behaviors of digital systems
 Supports design hierarchy as interconnections of components
 Can explicitly model the timing of digital systems
 Integration improves the design
– Lower parasitic = higher speed
– Lower power consumption
– Physically smaller
 Integration reduces manufacturing cost - (almost) no manual assembly

1.3.4 BASIC FEATURES OF VHDL

 CONCURRENCY.
 SUPPORTS SEQUENTIAL STATEMENTS.
 SUPPORTS FOR TEST & SIMULATION.
 STRONGLY TYPED LANGUAGE.
 SUPPORTS HIERARCHIES.
 SUPPORTS FOR VENDOR DEFINED LIBRARIES.
 SUPPORTS MULTIVALUED LOGIC.

1.3.4.1 CONCURRENCY:

 VHDL is a concurrent language.

 HDL differs with Software languages with respect to Concurrency only.
 VHDL executes statements at the same time in parallel as in Hardware.

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1.3.4.2 SUPPORTS SEQUENTIAL STATEMENTS

 VHDL supports sequential statements also. It executes one statement at a time in
sequence only.
 As the case with any conventional languages.

1.3.4.3 SUPPORTS FOR TEST & SIMULATION

 To ensure that design is correct as per the specifications, the designer has to write
another program known as “TEST BENCH”.
 It generates a set of test vectors and sends them to the design under test (DUT).
 Also gives the responses made by the DUT against specifications for correct results to
ensure the functionality.

1.3.4.4 STRONGLYTYPED LANGUAGE

 VHDL allows LHS & RHS operators of same type.
 Different types in LHS & RHS are illegal in VHDL.
 Allows different type assignment by conversion.
1.3.4.5 SUPPORTS HIRERCHIES
 Hierarchy can be represented using VHDL.
 Consider example of a Full-adder which is the top-level module, being composed of
three lower level modules i.e. Half-Adder and OR gate.

1.3.5 LEVELS OF ABSTRACTION

• Dataflow : gate level representation

• Structural : hierarchically interconnected components

• Behavioral : algorithm level representation

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1.3.5.1 DATA FLOW LEVEL:

 In this style of modeling the flow of data through the entity is expressed using concurrent
signal assignment statements.
 A Dataflow model specifies the functionality of the entity without explicitly specifying
its structure.
 This functionality shows the flow of information through the entity, which is expressed
primarily using concurrent signal assignment statements and block statements.
 The primary mechanism for modeling the dataflow behavior of an entity is using the
concurrent signal assignment statement.

1.3.5.2 SRUCTURAL LEVEL:

 In this style of modeling the entity is described as a set of interconnected statements.
 An entity is modeled as a set of components connected by signals, that is, as a net list.
 The behavior of the entity is not explicitly apparent from its model.
 The component instantiation statement is the primary mechanism used for describing
such a model of an entity.
 A component instantiated in a structural description must first be declared using a
component declaration.

1.3.5.3 BEHAVIORAL LEVEL:

The behavior of the entity is expressed using sequentially executed, procedural code, which
is very similar in syntax and semantics to that of a high level programming languages such as C
or Pascal.
 Built from “process” blocks
 Each block is sequential internally
o Can use variables
o Can use conditionals, loops, etc.
o Can maintain state
 The complete process is like a “big gate” Like gates, blocks operate concurrently
 This style of modeling specifies the behavior of an entity as a set of statements that are
executed sequentially in the specified order.

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 Process statement is the primary mechanism used to model the behavior of an entity.
 Process statement has a declarative part (before the keyword begin) and a statement part
(between the keywords begin and end process).
 The statements appearing within the statement part are sequential statements and are
executed sequentially.
1.3.6 VHDL IDENTIFIERS
• Identifiers are used to name items in a VHDL model.
• A basic identifier may contain only capital ‘A’ - ’Z’ , ‘a’ - ’z’, ‘0’ - ’9’, underscore
character ‘_’
• Must start with a alphabet.
• May not end with a underscore character.
• Must not include two successive underscore characters.
• Reserved word cannot be used as identifiers.
• VHDL is not case sensitive.

1.3.7 OBJECTS

There are three basic object types in VHDL

• Signal: represents interconnections that connect components and ports.
• Variable: used for local storage within a process.
• Constant: a fixed value.
The object type could be a scalar or an array.

1.3.8 COMPOSITE TYPES

There are two composite types
ARRAY:
• Contain many elements of the same type.
• Array can be either single or multidimensional.
• Single dimensional array are synthesizable.
• The synthesis of multidimensional array depends upon the synthesizer being used.
RECORD: Contain elements of different types.

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1.3.9 THE STD_LOGIC TYPE

 It is a data type defined in the std_logic_1164 package of IEEE library
 It is an enumerated type and is defined as type std_logic is (‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’,
‘L’, ‘H’,’-’)
 ‘u’ unspecified
 ‘x’ unknown
 ‘0’ strong zero
 ‘1’ strong one
 ‘z’ high impedance
 ‘w’ weak unknown
 ‘l’ weak zero
 ‘h’ weak one
 ‘-’ don’t care

1.3.10 SIGNAL ARRAY

– A set of signals may also be declared as a signal array which is a concatenated set of
signals.
– This is done by defining the signal of type bit_vector or std_logic_vector.
– bit_vector and std_logic_vector are types defined in the ieee.std_logic_1164 package.
– Signal array is declared as :
<type>(<range>)
Example:
signal data1:bit_vector(1 downto 0)
signal data2: std_logic_vector(7 down to 0);
signal address : std_logic_vector(0 to 15);

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1.3.11 OPERATORS:

The operators used in the VHDL as list out in the table

Table1.1: operators in VHDL

1.3.12 ENTITY
Entity - defines the interface (e.g., inputs/outputs)
to a ‘black box’ which performs a specific function.
 Entity describes the design interface.
 The interconnections of the design unit with the external world are enumerated.
 The properties of these interconnections are defined.

1.3.13 ARCHITECTURE

Architecture - one possible implementation

(or realization) of the “insides” of the “black box”.
An architecture may contain:

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• data declarations
• concurrent signal assignment
• component instantiations
• process blocks

 Architecture defines the functionality of the entity.

 It forms the body of the VHDL code.
 An architecture belongs to a specific entity.
 Various constructs are used in the description of the architecture.

1.3.14 SEQUENTIALPROCESSING (PROCESS)

 Process defines the sequential behavior of entire or some portion of the design.
 Process is synchronized with the other concurrent statements using the sensitivity list or
wait statement.
 Statements, which describe the behavior in a process, are executed sequentially.
 All processes in an architecture behave concurrently.
 Simulator takes Zero simulation time to execute all statements in a process.
 Process repeats forever, unless suspended.

1.3.15 FUNCTION

 Unlike procedure, a function cannot change its argument and can only return a value.
 Function parameters can only be of type constant or signal. The mode is always in.
Default class is constant.
 An impure function may return different values even if the parameters are the same.
Whereas a pure function always returns the same values as parameters.
 A function has to have a return statement with an expression the value of the expression
defines the result returned by the function.

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1.3.15.1 Data Types Supported

• bit A: in bit;

• bit_vector B: in bit_vector(7 downto 1);

• constants ‘1’, or ‘0’, or “10010”

• bitvec B: bitvec;

• integer C: integer;

• real C: real;

• std_logic D: std_logic; (IEEE library)

• User defined

1.3.16 Designing with VHDL

1.3.16.1 Design Process:

1. Design entry (VHDL)

2. Testing (VHDL test vector simulation)

3. Synthesis (FPGA, standard cell, full custom)

4. Testing (logic analyzer)

1.3.16.2 Cutting Edge Technology

• FPGA (can be found in many systems)

• VHDL (1998 DOD requires all ASIC suppliers to deliver VHDL description of the ASIC
and their sub components at both the behavioral level and structural level)

• Put FPGA and VHDL in your resume!

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1.3.17 PROBLEMS IN VHDL:

• No generic packages
• No function pointers
• File I/O is pretty clumsy ...
• No math library yet
• can use C-interface
• No standard package for low level simulation
• No support for high level simulation with message queues
• Arbitrary data types make user-interface a problem
• Just too complex!

1.3.18 VLSI APPLICATIONS:

VLSI is an implementation technology for electronic circuitry - analogue or digital

• It is concerned with forming a pattern of interconnected switches and gates on the surface
of a crystal of semiconductor

• Microprocessors

– personal computers

– microcontrollers

• Memory - DRAM / SRAM

• Special Purpose Processors - ASICS (CD players, DSP applications)

• Optical Switches

• Has made highly sophisticated control systems mass-producable and therefore cheap

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2.1 HOW TO CREATE A PROJECT IN XILINX

2.1.1 Starting the ISE Software
To start ISE, double-click the desktop icon,

or start ISE from the Start menu by selecting:

Start → All Programs → Xilinx ISE 10.1→ Project Navigator
Note: Your start-up path is set during the installation process and may differ from the one above.

2.1.2 Accessing Help

At any time during the tutorial, you can access online help for additional information about the
ISE software and related tools.
To open Help, do either of the following:
• Press F1 to view Help for the specific tool or function that you have selected or highlighted.
• Launch the ISE Help Contents from the Help menu. It contains information about creating and
maintaining your complete design flow in ISE.

Figure 2.1.1: ISE Help Topics

2.1.3 Create a New Project

Create a new ISE project which will target the FPGA device on the Spartan-3 Startup Kit demo
board.

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To create a new project:

1. Select File > New Project... The New Project Wizard appears.
2. Type tutorial in the Project Name field.
3. Enter or browse to a location (directory path) for the new project. A tutorial subdirectory is
created automatically.
4. Verify that HDL is selected from the Top-Level Source Type list.
5. Click Next to move to the device properties page.
6. Fill in the properties in the table as shown below:
♦Product Category: All
♦ Family: Spartan3
♦ Device: XC3S200
♦ Package: FT256
♦ Speed Grade: -4
♦ Top-Level Source Type: HDL
♦ Synthesis Tool: XST (VHDL/Verilog)
♦ Simulator: ISE Simulator (VHDL/Verilog)
♦ Preferred Language: Verilog (or VHDL)
♦ Verify that Enable Enhanced Design Summary is selected.
Leave the default values in the remaining fields.
When the table is complete, your project properties will look like the following:

7. Click next to proceed to the Create New Source window in the New Project Wizard. At the
end of the next section, your new project will be complete.

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Figure 2.1.2: Project Device Properties

2.1.4 Create an HDL Source

In this section, you will create the top-level HDL file for your design. Determine the language
that you wish to use for the tutorial. Then, continue either to the “Creating a VHDL Source”
section below, or skip to the “Creating a Verilog Source” section.

2.1.5 Creating a VHDL Source

Create a VHDL source file for the project as follows:
1. Click the New Source button in the New Project Wizard.
2. Select VHDL Module as the source type.
3. Type in the file name counter.
4. Verify that the Add to project checkbox is selected.
5. Click Next.
6. Declare the ports for the counter design by filling in the port information as shown below:

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Figure 2.1.3 define module

7. Click next, and then Finish in the New Source Wizard - Summary dialog box to complete the
new source file template.
8. Click Next, then Next, then Finish.
The source file containing the entity/architecture pair displays in the Workspace, and the counter
displays in the Source tab, as shown below:

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Figure 2.1.4: New Project in ISE

2.1.6 Using Language Templates (VHDL)

The next step in creating the new source is to add the behavioral description for the counter. To
do this you will use a simple counter code example from the ISE Language Templates and
customize it for the counter design.
1. Place the cursor just below the begin statement within the counter architecture.
2. Open the Language Templates by selecting Edit → Language Templates…
Note: You can tile the Language Templates and the counter file by selecting Window → Tile
Vertically to make them both visible.
3. Using the “+” symbol, browse to the following code example:
VHDL → Synthesis Constructs → Coding Examples → Counters → Binary →
Up/Down Counters → Simple Counter
4. With Simple Counter selected, select Edit → Use in File, or select the Use Template in
File toolbar button. This step copies the template into the counter source file.

5. Close the Language Templates.

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2.1.7 Final Editing of the VHDL Source

1. Add the following signal declaration to handle the feedback of the counter output below the
architecture declaration and above the first begin statement:
signal count_int : std_logic_vector(3 downto 0) := "0000";
2. Customize the source file for the counter design by replacing the port and signal name
placeholders with the actual ones as follows:
♦ replace all occurrences of <clock> with CLOCK
♦ replace all occurrences of <count_direction> with DIRECTION
♦ replace all occurrences of <count> with count_int
3. Add the following line below the end process; statement:
COUNT_OUT <= count_int;
4. Save the file by selecting File → Save.

2.1.8 Design Simulation

Verifying Functionality using Behavioral Simulation. Create a test bench waveform containing
input stimulus you can use to verify the functionality of the counter module. The test bench
waveform is a graphical view of a test bench.
Create the test bench waveform as follows:
1. Select the counter HDL file in the Sources window.
2. Create a new test bench source by selecting Project → New Source.
3. In the New Source Wizard, select Test Bench Wave Form as the source type, and type
counter_tbw in the File Name field.
4. Click Next.
5. The Associated Source page shows that you are associating the test bench waveform with the
source file counter. Click Next.
6. The Summary page shows that the source will be added to the project, and it displays the
source directory, type, and name. Click Finish.
7. You need to set the clock frequency, setup time and output delay times in the Initialize
Timing dialog box before the test bench waveform editing window opens.

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The requirements for this design are the following:

♦ The counter must operate correctly with an input clock frequency = 25 MHz.
♦ The DIRECTION input will be valid 10 ns before the rising edge of CLOCK.
♦ The output (COUNT_OUT) must be valid 10 ns after the rising edge of CLOCK.
The design requirements correspond with the values below.
Fill in the fields in the Initialize Timing dialog box with the following information:
♦ Clock High Time: 20 ns.
♦ Clock Low Time: 20 ns.
♦ Input Setup Time: 10 ns.
♦ Output Valid Delay: 10 ns.
♦ Offset: 0 ns.
♦ Global Signals: GSR (FPGA)
Note: When GSR(FPGA) is enabled, 100 ns. is added to the Offset value automatically.
♦ Initial Length of Test Bench: 1500 ns.

2.2 HOW TO CREATE A PROJECT IN MODELSIM:

2.2.1 INTRODUCTION:
ModelSim is a verification and simulation tool for VHDL, Verilog, System Verilog, and mixed
language designs.
This chapter provides a brief conceptual overview of the ModelSim simulation environment. It is
divided into fourt opics, which you will learn more about in subsequent lessons.
 Basic simulation flow
 Project flow
 Multiple library flow
 Debugging tools

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2.2.2 BASIC SIMULATION FLOW:

The following diagram shows the basic steps for simulating a design in ModelSim.

Figure 2.2.1 Basic Simulation Flow - Overview Lab

 Creating the Working Library

In ModelSim, all designs are compiled into a library. You typically start a new simulation in
ModelSim by creating a working library called "work". "Work" is the library name used by the
compiler as the default destination for compiled design units.
 Compiling Your Design
After creating the working library, you compile your design units into it. The ModelSim library
format is compatible across all supported platforms. You can simulate your design on any
platform without having to recompile your design.
 Loading the Simulator with Your Design and Running the Simulation
With the design compiled, you load the simulator with your design by invoking the simulator on
a top-level module (Verilog) or a configuration or entity/architecture pair (VHDL).
Assuming the design loads successfully, the simulation time is set to zero, and you enter a run
command to begin simulation.

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 Debugging Your Results

If you don’t get the results you expect, you can use ModelSim’s robust debugging environment
to track down the cause of the problem.

2.2.3 CREATE THE WORKING DESIGN LIBRARY:

Before you can simulate a design, you must first create a library and compile the source code
into that library.
1. Create a new directory and copy the design files for this lesson into it.
Start by creating a new directory for this exercise (in case other users will be working with these
lessons).
Verilog: Copy counter.v and tcounter.v files from
/<install_dir>/examples/tutorials/verilog/basicSimulation to the new directory.
VHDL: Copy counter.vhd and tcounter.vhd files from
/<install_dir>/examples/tutorials/vhdl/basicSimulation to the new directory.
2. Start ModelSim if necessary.
a. Type vsim at a UNIX shell prompt or use the ModelSim icon in Windows.
Upon opening ModelSim for the first time, you will see the Welcome to ModelSim
dialog. Click Close.
b. Select File > Change Directory and change to the directory you created in step 1.
3. Create the working library.
a. Select File > New > Library.
This opens a dialog where you specify physical and logical names for the library (Figure 2.2.2).
You can create a new library or map to an existing library. We’ll be doing the former.
b. Type work in the Library Name field (if it isn’t already entered automatically).

c. Click OK.

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Figure 2.2.2 The Create a New Library Dialog

ModelSim creates a directory called work and writes a specially-formatted file named _info into
that directory. The _info file must remain in the directory to distinguish it as a ModelSim library.
Do not edit the folder contents from your operating system; all changes should be made from
within ModelSim.
ModelSim also adds the library to the list in the Workspace (Figure 2.2.3) and records the library
mapping for future reference in the ModelSim initialization file (modelsim.ini).

Figure 2.2.3. work Library in the Workspace

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When you pressed OK in step 3c above, the following was printed to the Transcript:
vlib work
vmap work work
These two lines are the command-line equivalents of the menu selections you made. Many
command-line equivalents will echo their menu-driven functions in this fashion.

2.2.4 COMPILE THE DESIGN:

With the working library created, you are ready to compile your source files.
You can compile by using the menus and dialogs of the graphic interface, as in the Verilog
example below, or by entering a command at the ModelSim> prompt.
1. Compile counter.v and tcounter.v.
a. Select Compile > Compile. This opens the Compile Source Files dialog (Figure 2.2.4).
If the Compile menu option is not available, you probably have a project open. If so,
close the project by making the Workspace pane active and selecting File > Close from the
menus.
b. Select both counter.v and tcounter.v modules from the Compile Source Files dialog
and click Compile. The files are compiled into the work library.
c. When compile is finished, click Done.

Figure 2.2.4 Compile Source Files Dialog

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2. View the compiled design units.

a. On the Library tab, click the ’+’ icon next to the work library and you will see two
design units (Figure 2.2.5). You can also see their types (Modules, Entities, etc.) and
the path to the underlying source files (scroll to the right if necessary).

Figure 2.2.5 Verilog Modules Compiled into work Library

2.2.5 LOAD THE DESIGN:

1. Load the test_counter module into the simulator.
a. In the Workspace, click the ‘+’ sign next to the work library to show the files
contained there.
b. Double-click test_counter to load the design.
You can also load the design by selecting Simulate > Start Simulation in the menu
bar. This opens the Start Simulation dialog. With the Design tab selected, click the
’+’ sign next to the work library to see the counter and test_counter modules. Select
the test_counter module and click OK (Figure 2.2.6).

When the design is loaded, you will see a new tab in the Workspace named sim that displays the
hierarchical structure of the design (Figure 2.2.7). You can navigate
within the hierarchy by clicking on any line with a ’+’ (expand) or ’-’ (contract)
icon. You will also see a tab named Files that displays all files included in the
design.

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Figure 2.2.6 Loading Design with Start Simulation Dialog

When the design is loaded, you will see a new tab in the Workspace named sim that displays the
hierarchical structure of the design (Figure 2.2.7). You can navigate within the hierarchy by
clicking on any line with a ’+’ (expand) or ’-’ (contract) icon. You will also see a tab named
Files that displays all files included in the design.

Figure 2.2.7 Workspace sim Tab Displays Design Hierarchy

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2. View design objects in the Objects pane.

a. Open the View menu and select Objects. The command line equivalent is: view
objects
The Objects pane (Figure 2.2.8) shows the names and current values of data objects in the
current region (selected in the Workspace). Data objects include signals, nets, registers, constants
and variables not declared in a process, generics, and parameters.

Figure 2.2.8 Object Pane Displays Design Objects

You may open other windows and panes with the View menu or with the view command.
2.2.6 RUN THE SIMULATION:
Now you will open the Wave window, add signals to it, then run the simulation.
1. Open the Wave debugging window.
a. Enter view wave at the command line.
You can also use the View > Wave menu selection to open a Wave window.

The Wave window is one of several windows available for debugging. To see a list of the other
debugging windows, select the View menu. You may need to move or resize the windows to
your liking. Window panes within the Main window can be zoomed to occupy the entire Main
window or undocked to stand alone.
2. Add signals to the Wave window.
a. In the Workspace pane, select the sim tab.
b. Right-click test_counter to open a popup context menu.
c. Select Add > Add All Signals to Wave (Figure 2.2.9).

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All signals in the design are added to the Wave window.

Figure: 2.2.9. Using the Popup Menu to Add Signals to Wave Window

3. Run the simulation.

a. Click the Run icon in the Main or Wave window toolbar.
The simulation runs for 100 ns (the default simulation length) and waves are drawn in the Wave
window.
b. Enter run 500 at the VSIM> prompt in the Main window.
The simulation advances another 500 ns for a total of 600 ns (Figure 2.2.10).

Figure: 2.2.10 Waves Drawn in Wave Window

c. Click the Run -All icons on the Main or Wave window toolbar.

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The simulation continues running until you execute a break command or it hits a statement in
your code (e.g., a Verilog $stop statement) that halts the simulation.
d. Click the Break icon. The simulation stops running.

2.2.7 MAIN WINDOW:

The Main window is composed of a number of "panes" and sub-windows that display various
types of information about your design, simulation, or debugging session. You can also access
other tools from the Main window that display in stand-alone windows (e.g., the Dataflow
window).

Figure: 2.2.11 the Main Window

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The following table describes some of the key elements of the Main window.

Table 2.2.1 The Main Window

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3. VARIABLE MULTI-PHASE TRAFFIC LIGHT CONTROLLER

DESIGN AND ANALYSIS

3.1 WHOLE DESIGN THROUGH:

The intelligent traffic light controller this paper provides can be applied both in common
intersections and multiple branches intersections. It needs to design external input pins on the
controller in order to realize the aim of adjusting multi-phase based on actual traffic flow. 2-
phase, 3-phase and 4-phase play important roles in practical traffic control, therefore, this system
provides their operation modes as shown in Figure 3.1.

Both master and slave branches have green, red, yellow and left-hand turn lights. When it
comes to 2-phase operation mode, green, red and yellow lights work both on master and slave
branches. In 3-phase operation mode, green, red, yellow and left-hand turn lights work on master
branch, but only green, red and yellow lights work in slave branch. In 4-phase operation mode,
all the lights work in master and slave branches. The durations of all kinds of lights are variable,
the specific times are set by external input pins. Both master and slave branches have the LEDs
to display the countdown of running light. This controller has reset and hold input signals. When
the reset signal is valid, all lights extinguish and all the LEDs show noting both in master and
slave branches. Meanwhile, the controller receives the settings of running time and phase
number. When the reset signal is invalid, the controller began to run with the new settings. When
the hold signal is effective, all the LEDs remain unchanged and all the red lights work both on
master and slave branches. When the hold signal is ineffective, the controller continue to run
with former state.

3.2 ANALYSIS OF THE RUNNING STATE:

In actual traffic control, green, yellow, red lights work in turn circularly. According to the
different phase, the left-hand turn light of the master and slave branches choose to shows

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between green and yellow lights. Generally speaking, the total durations of green, left-hand turn
and yellow light equal to the duration of red light. For the convenience of programming and
debugging, the transition control can be achieved by finite state machine.

Figure 3.1. Multi-phase operation modes

3.3 STRUCTURE OF THE SYSTEM:

The main functions components of the system are traffic lights controller, countdown controller
and LED display controller. The chart of system structure is shown in Figure 3.2. Main controller
is the core of the system, all the signals of traffic lights both on master and slave branches are
generated by the main controller. According to different value of phase selection, all traffic lights
run as the modes shown in Figure 3.1. Meanwhile, the countdown numbers are provided and sent
to LED display controller. Benchmark clock of the system is provided by the external circuit. All
the lights both on the master and slave branches are timed for the S unit. Both the LEDs on
master and slave branches display the remaining running time in countdown form. Usually, the
duration of red light is the longest, the sum time of green, left-hand turn and yellow lights equals
to the red light’.

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Figure 3.2. Structure of the system

3.4 HIERARCHICAL DESIGN THOUGHT:

For programming convenience by VHDL language, the system is divided into two
hierarchies, top module and sub-modules, as shown in Figure 3.3. The main controller realized
by the top module includes those input signals such as benchmark clock signal, phase selection
signal, time setting signal, hold signal and reset signal, and output signals such as traffic light
control signals, countdown signals and so on. It is sub-modules that realize traffic light control
and LED display of countdown.

Figure 3.3. Structure of Hierarchical Design

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COMONENT DIAGRAM:

Figure3.4 : component diagram

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4. DESIGN DESCRIPTION:

4.1 ALGORITHM:

 Initially all red lights will be “ON” (south, west, north, east, pedestrian).
 Green lights of will be”ON”, right, left & straight paths are free for traffic.
 Yellow phase is split as yellow1 & yellow2, in yellow1 phase yellow lights will be on
and respective left & pedestrian paths are free for traffic.
 In yellow2 phase only yellow lights will be “ON”.
 Same flow is repeated for all four paths. (South, west, north, east).

To start the traffic light controller

1. Initially the red light of all the directions is ON.

2. Traffic starts from the south direction; hence the green light of south direction goes ON.
The signals that are ON now are:-
 Ls (left south)-‘1’.
 Rs (right south)-‘1’.
 Ss (straight south)-‘1’.
 Le (left east)-‘1’.
 Red_w (red west)-‘1’.
 Red_n (red north)-‘1’.
 Red_e (red east)-‘1’.
 Ps_r (pedestrian south red)-‘1’.
 Pw_r (pedestrian west red)-‘1’.
 Pn_r (pedestrian north red)-‘1’.
 Pe_r (pedestrian east red)-‘1’.

Similarly when orange light of south direction is ON then the signals that are ON, now are

 Is (left south)-‘1’.
 Ys (yellow south)-‘1’.
 Le (left east)-‘1’.
 Red_w (red west)-‘1’.

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 Red_n (red north)-‘1’.

 Red_e (red east)-‘1’.
 Ps_r (pedestrian south red)-‘1’.
 Pw_r (pedestrian west red)-‘1’.
 Pn_r (pedestrian north red)-‘1’.
 Pe_r (pedestrian east red)-‘1’.

Similarly when red light of south direction is ON then the signals that are ON,now are

 Ls (left south)-‘1’.
 Red_w (red west)-‘1’.
 Red_n (red north)-‘1’.
 Red_e (red east)-‘1’.
 Ps_r (pedestrian south red)-‘1’.
 Pw_r (pedestrian west red)-‘1’.
 Pn_r (pedestrian north red)-‘1’.
 Pe_r (pedestrian east red)-‘1’.

During this time all ways are blocked for 1 second except left south (is-‘1’) and so on. After that
it goes clockwise for all direction (i.e.:-south then west then north then east) similarly.

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4.2 FLOW CHART:

Figure 4.1: flow chart for traffic light contoller

Initially all red lights will be “ON”(south, west, north, east, pedestrian). Green lights of will be
“ON”, right, left & straight paths are free for traffic. Yellow phase is split as yellow1 & yellow2,
in yellow1 phase yellow lights will be on and respective left & pedestrian paths are free for
traffic. In yellow2 phase only yellow lights will be “ON”. Same flow is repeated for all four
paths. (South, west, north, east).

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4.3 STATE TRANSITION CHART:

A state diagram is a type of diagram used in computer science and related fields to describe the
behavior of systems. State diagrams require that the system described is composed of a finite
number of states; sometimes, this is indeed the case, while at other times this is a reasonable
abstraction. There are many forms of state diagrams, which differ slightly and have different
semantics.

Figure 4.2: State transition chart for traffic light controller

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5.1 RESULTS:

5.1.1 Out put of Traffic Llight Controller

Initially all red lights will be “ON” (south, west, north, east and pedestrian) as shown in the
figure below. Green lights of will be”ON”, right, left & straight paths are free for traffic. Yellow
phase is split as yellow1 & yellow2, in yellow1 phase yellow lights will be on and respective left
& pedestrian paths are free for traffic. In yellow2 phase only yellow lights will be “ON”. Same
flow is repeated for all four paths (south, west, north, and east).

The input signals which are used are clk and rst.

The output signals are used are:

Ls (left south), Le (left east), lw (left west), ln (left north),

Rs (right south), Rn (right north), Rw (right west), Re (right east),

Ss (straight south), Sn (straight north), Se (straight east), Sw (straight west),

Red_w (red west), Red_n (red north) Red_e (red east), Red_s (red south),

Ps_r (pedestrian south red), Pw_r (pedestrian west red), Pn_r (pedestrian north red),

Pe_r (pedestrian east red),

Ps_g (pedestrian south green), Pw_g (pedestrian west green) Pn_g (pedestrian north green),
Pe_g (pedestrian east green),

Ys (yellow south), Yn (yellow north), Yw (yellow west) and Ye (yellow east)

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Contd…….

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Figure5.1: Output waveform of traffic light controller

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5.1.2 Circuits obtained from code:

The following are the circuits obtained by generating the code using XILINX.

 Figure 5.2 gives the list of inputs and outputs used &
 Figure 5.3 gives the detailed circuit

Figure 5.2: top level symbol

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Figure 5.3: circuit model obtained by XILINX

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5.2 CONCLUSIONS:

The variable multi-phase (2-phase, 3-phase and 4- phase) intelligent traffic light controller can be
realized by establishing system model, programming with VHDL language, and simulating with
XILINX. This design thought can reduce the design cycle, improve the reliability and flexibility.
The controller can be made into embedded circuit board to satisfy the need to update the valve of
control phase according to the actual traffic flow in city's traffic intersections.

The improvement of town traffic condition is largely dependent on the modern ways of traffic
management and control. Advanced traffic signal controllers and control system contribute to the
improvement of the traffic problem. The intelligent of traffic signal controller is introduced in
this project with powerful functions.

FUTURE SCOPE:

Traffic light controller is implemented on SPARTAN-3 TRAINER using traffic light interface
module. There are simple rules for traffic lights on one mode, and complex ways of regulating a
whole infrastructure of them. It is necessary to adjust general algorithms. Simple dumped the
whole program code of “DESIGN OF INTELLIGENT TRAFFIC LIGHT CONTROLLER
BASED ON VHDL” in the SPARTAN-3 TRAINER kit. Through the traffic light interface
module we can implement this as a real time TLC system.

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5.3 BIBLOGRAPHY

[1] Huancheng Liu, Zhiyong Liu, “A New Kind Of Multi- Microprocessors System Based
Traffic Signal Controller”, Instrument Technique and Sensor, 2003, Vol. 8. pp.15- 19.
[2] Zhongsu Wang, “Application of PLC in the City Traffic Light Control System”, Instrument
Technique and Sensor,2003 Vol. 6, pp.36-38.
[3] Hong Y S, Hyunsoo J,“New electro sensitive traffic light using fuzzy neural network ”,
Fuzzy Systems IEEE Transactions Digital Object Identifier, Vol.4, No. 6,1999, pp.759-767.
[4] Baoxia Cui, Ji-ping Yang, Chunfeng Xu, “New strategy in optimization of urban traffic
signal timing controller”, Journal of Shenyang University of Technology, Vol. 29, No. 5,2007,
pp: 554-
557.
[5] Haiying Zhang, Yu Zhen, CHENYan-ping, “Application of Fuzzy Control Intelligent Traffic
Lights Monitoring System”, Computer Technology and Development, Vol. 18, No. 3, 2008, pp:
181-183.
[6] [Findler and Stapp, 1992] Findler, N. and Stapp, J. (1992). A distributed approach to
optimized control of street traffic signals. Journal of Transportation Engineering, 118-1:99–110.
[7] M. McDonald and N.B. Hounsel : Road Traffic Control : TRANSYT and SCOOT p. 400-
408 in concise encyclopedia of Traffic and Transportation Systems, Editor M. Papageorgiou,
Pergamon Press (1991).

[8] M. Patriksson: The traffic assignment problem : models and methods. VSP BV Utrecht,
(1994).

[9] R.-J. van Egmond and G.J. Olsder : The maxplus algebra applied to synchronization of traffic
light processes. Actes de la 26`eme ´ecole de printemps d’informatique th´eorique, Noirmoutier
(1998).

[10] N. H. Gartner: Road Traffic Control: Progression Methods p. 387-391 in concise

encyclopedia
of Traffic and Transportation Systems, Editor M. Papageorgiou, Pergamon Press (1991).

[11] Digital design principles and practices-john F.wakerly_3rd edition.

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[12] “Intelligent Transportation Systems in the Transportation Equity Act for the 21st Century,”
Federal Highway Administration Publication No. FHWA-jpo-99-040.
[13] “National ITS Program Plan: A Ten-Year Vision,” ITS America, Washington, D.C.,
January 2002.
[14] Obenberger, J., and W.H. Kraft, “Surface Transportation Systems: The Role of Traffic
Management Centers.”
[15] A dynamic and automatic traffic light control expert system for solving the road congestion
problem by W. Wen

[16] IDUTC: An Intelligent Decision-Making System for Urban Traffic-Control Applications by

M. Patel and N. Ranganathan
[17] Fuzzy System Handbook by Cox
[18] VHDL Analyzer User's Manual, Intermetrics, Inc., 1987.
[19] VHDL Language Reference Manual, Intermetrics, Inc., 1987.
[20] VHDL Simulator User's Manual, Intermetrics, Inc., 1987.

[21] www.sciencedirect.com

[22] www.IEEE.org

[23] en.wikipedia.org

[24] www.vhdl.org

[25] www.gmvhdl.com

[26] http://www.doulos.com

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