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Qb for Ec1404 Vlsi Lab

Qb for Ec1404 Vlsi Lab

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VLSI lab, semester 07, Anna University
VLSI lab, semester 07, Anna University

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Published by: Chandramouleeswaran Sarma on Dec 01, 2010
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Questionbank for EC1404 VLSI lab
1.Design a half-adder and full-subtractor in verilog and also simulate the sameusing Xilinx-ISE simulator.2.Design a half-subtractor and full-adder in verilog and also simulate the sameusing Xilinx-ISE simulator.3.Implement an 8:1 MUX in verilog and also simulate the same using Xilinx-ISEsimulator.4.Implement an 8:1 MUX using 4:1 MUX and also simulate the same using Xilinx-ISE simulator.5.Design 3 to 8 decoder in verilog and also simulate the same using Xilinx-ISEsimulator.6.Design a 4 to 16 decoder in verilog and also simulate the same using Xilinx-ISEsimulator.7.Design 1:4 DEMUX and 1:8 DEMUX using verilog.8.Write a verilog program to convert a given BCD number to seven segmentdisplay in common cathode and also simulate the same using Xilinx-ISEsimulator.9.Write a verilog program to convert a given BCD number to seven segmentdisplay in common anode mode and also simulate the same using Xilinx-ISEsimulator.10.Write a verilog program to convert a given weighted-code to cyclic code and alsosimulate the same using Xilinx.11.Write a verilog program to convert a given cyclic code to weighted-code and alsosimulate the same using Xilinx.12.Write a verilog program to convert a given weighted-code to self-complementingcode and also simulate the same using Xilinx.13.Write a verilog program to convert a given self-complementing code to weighted-code and also simulate the same using Xilinx.14.Write a verilog program to implement a Full adder using Half adder in verilog andalso simulate the same using Xilinx-ISE simulator.15.Write a verilog program to design a 4-bit magnitude comparator using 2-bitmagnitude comparator and also simulate the same using Xilinx-ISE simulator.16.Write a verilog program to design a 4 bit Ripple carry adder and also simulate thesame using Xilinx-ISE simulator.17.Write a verilog program to design an 8:3 encoder and also simulate the sameusing Xilinx-ISE simulator.18.Design and simulate an asynchronous 4bit counter using JK Flip Flop with activelow CLEAR signal using Xilinx-ISE simulator.19.Design and simulate a synchronous 4 bit counter using T Flip Flop with activehigh CLEAR signal using Xilinx-ISE simulator.20.Write a verilog program to convert JK flip flop into SR, T and D flip flop and alsosimulate the same using Xilinx-ISE simulator.21.Design a parallel-in-parallel-out shift register using verilog and also simulate thesame using Xilinx-ISE simulator.

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