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Solutions to 45 Probs

Solutions to 45 Probs

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VLSI lab, semester 07, Anna University
VLSI lab, semester 07, Anna University

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Published by: Chandramouleeswaran Sarma on Dec 01, 2010
Copyright:Attribution Non-commercial


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1) Half adder and Full subtractor-lab prog2) Half subtractor and Full adder-lab prog3) 8x1 Mux using behavioral modelling
module mux(x,s,y);input [7:0]x;input [2:0]s;output y;reg y;always@(x or s)beginif(s==0)y=x[0];else if(s==1)y=x[1];else if(s==2)y=x[2];else if(s==3)y=x[3];else if(s==4)y=x[4];else if(s==5)y=x[5];else if(s==6)y=x[6];else if(s==7)y=x[7];endendmodulemodule testbench();reg [7:0]x;reg [2:0]s;wire y;mux m1(x,s,y);initialbeginx=8'b00000001;s=3'd0;#10 x=8'b00000010;s=3'd1;#10 $finish;endendmodule
4) 8x1 Mux using 4x1 Mux
module mux4(i,s,y);input [3:0]i;input [1:0]s;output y;reg y;always @(i or s)case(s)2'b00: y=i[0];2'b01: y=i[1];2'b10: y=i[2];2'b11: y=i[3];endcaseendmodulemodule mux8(x,sel,y0);input [7:0]x;input [2:0]sel;output y0;wire y1,y2;mux4 m1(x[3:0],sel[1:0],y1);mux4 m2(x[7:4],sel[1:0],y2);assign y0=sel[2]?y2:y1;endmodulemodule testbench();reg [7:0]x;reg[2:0]sel;wire y0;mux8 m3(x,sel,y0);initialbeginx=8'b11111111;sel=3'd0;#10 x=8'b00000000;sel=3'd0;#10 $finish;endendmodule
5) 3x8 Decoder-lab prog6) 4x16 Decoder
module dec4x16(x,y);input [3:0]x;output [15:0]y;assign y[0]= ~x[0] & ~x[1] & ~x[2] & ~x[3];assign y[1]= ~x[0] & ~x[1] & ~x[2] & x[3];assign y[2]= ~x[0] & ~x[1] & x[2] & ~x[3];assign y[3]= ~x[0] & ~x[1] & x[2] & x[3];assign y[4]= ~x[0] & x[1] & ~x[2] & ~x[3];assign y[5]= ~x[0] & x[1] & ~x[2] & x[3];
assign y[6]= ~x[0] & x[1] & x[2] & ~x[3];assign y[7]= ~x[0] & x[1] & x[2] & x[3];assign y[8]= x[0] & ~x[1] & ~x[2] & ~x[3];assign y[9]= x[0] & ~x[1] & ~x[2] & x[3];assign y[10]= x[0] & ~x[1] & x[2] & ~x[3];assign y[11]= x[0] & ~x[1] & x[2] & x[3];assign y[12]= x[0] & x[1] & ~x[2] & ~x[3];assign y[13]= x[0] & x[1] & ~x[2] & x[3];assign y[14]= x[0] & x[1] & x[2] & ~x[3];assign y[15]= x[0] & x[1] & x[2] & x[3];endmodulemodule testbench();reg [3:0]x;wire [15:0]y;dec4x16 test(x,y);initialbeginx=4'b0000;#10 x=4'b0001;#10 x=4'b0010;......#10 x=4'b1111;#10 $finish;endendmodule
7) 1:8 Demux (1:4 demux-lab prog)
module demux8(x,s,y);input x;input [2:0]s;output [7:0]y;reg [7:0]y;always @ (x or s)beginy=8'd0;case(s)3'b000:y[0]=x;3'b001:y[1]=x;3'b010:y[2]=x;3'b011:y[3]=x;3'b100:y[4]=x;3'b101:y[5]=x;3'b110:y[6]=x;3'b111:y[7]=x;endcaseend

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/*********** DO NOT ALTER ANYTHING BELOW THIS LINE ! ************/ var s_code=s.t();if(s_code)document.write(s_code)//-->