Parameterized Models for a RF Chip-To-Substrate Interconnect
Ingo Doerr1, Lih-Tyng Hwang2, Grit Sommer1, Hermann Oppermann1, Li Li2, Michael
Petras2, Sabine Korf1, Faical Sahli1, Tom Myers2, Mel Miller2 and Werner John1
1
Fraunhofer IZM
Gustav-Meyer-Allee 25, D-13355 Berlin
2
Motorola, SPS
2100 E. Elliot Road, Tempe, AZ 85284
Abstract
Skyrocketing growth in the cellular personal
communications services (PCS) sector has fueled the needs
for higher density, more functionality, and greater
performance on both handset and basestations. Third
generation wireless standards, which require hardware
upgrades, loom on the horizon. RF component suppliers are
scrambling to find solutions at the IC, package, and PCB
levels to meet these challenges. RF module packaging is
considered as one of the low cost solutions to the future
wireless products. One of the critical design needs for RF
interconnects is to understand the electrical performance of
wire bond (the RF interconnect of choice) at and above
frequency of interest, and to determine the performance limit
for the wire bond chip-to-substrate interconnect. The
availability of design kit or library would result in a
substantial reduction in design cycle times. Using wire bond
as example, this paper illustrates the developmental stages
that turn electromagnetic characteristics of a physical
structure into design library. Fullwave simulation using
Ansoft HFSS and compact models extraction using
optimization tool for wire bond will be shown, followed by
in-depth discussions of wire bond parameterized models.
Validation of parameterized model by measurement will be
presented.
Introduction
RF module packaging has many advantages: favorable
pricing power being the most important one, as opposed to
cost-based pricing at the sum of the individual ICs and
embedded passives costs. The module packaging can also
benefit the system integrators who are less skillful in RF
design and skills. This ease of use leads to proliferation of
RF module demands. Design tools or libraries for module are
one of the critical paths that enable a full adoption of the
module technology.
In this paper, the parameterized electrical compact (RLC)
models of wire bonds (the RF interconnect of choice) are
shown. Since interconnects are relatively independent of the
substrate of choice, development of interconnect models need
not be repeated as substrate of choice changes. Since LTCC
allows an easy implementation of different die height (or
thickness) using cavity, it is used in wire bond interconnect
models development. Using mainly single wire bonds as
example, the design tool development methodology is
illustrated. First, the design space and Design of Experiment
(DOE) for wire bonds are described, followed by Ansoft
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HFSS simulation, feed de-embedding technique, and the
optimization routine used to obtain the R, L, C equivalent
circuits. Experimental validation, including design of
interconnect test die and LTCC test substrate, is also
described.
Wire Bond Simulation
The design space (main independent factors and their
ranges) of wire bonds was determined first. Experimental
design principles were then practiced to minimize the number
of simulation runs.
After the DOE was set up, Ansoft’s high frequency
structure simulator (HFSS) was employed to obtain the full-
wave characteristics of the wire bonds. Since the full wave
simulation requires a uniform wave front, port feeds were
needed and included in the simulation. The feed was then de-
embedded to obtain wire(s) only characteristics in S-
parameters. R, L, and C of the wire bond compact models
were extracted by optimization tool (Serenade from Ansoft)
using the wire only S-parameters.
Design of Experiment
In order to investigate the impacts of geometrical factors
on the electrical behavior of a component (wire bond, for
example) in an efficient way, an experimental design (DOE)
was set up. Having chosen the main factors and their
appropriate levels, the DOE runs (in full or fractional
factorial, depending on the number of runs) were simulated
using Ansoft’s HFSS.
Single Wire (Ball-Wedge)
The main independent factors of the single wire bond are
the span of the wire (Span), the elevation difference between
the first and the second bonds (DH), the maximum wire loop
height from the first bond (MH) and the type of bonding, e.g.
ball-wedge and wedge-wedge.
The type of wire bonding determines the location where
the maximum loop height occurs. For ball-wedge bonding, it
is assumed that the maximum loop height occurs about one-
third the span. In Figure 1, the critical parameters of a ball-
wedge bonding are illustrated. Since the glob top affects the
capacitance of the wire bond, the dielectric properties (εr,
tanδ) were also entered as critical parameter (see Table 1). In
this paper, the wires are made of Au, and the diameter of the
wires is set to be 1 mil (25.4 µm).
2001 Electronic Components and Technology Conference
Figure 1: Geometry and relevant Parameter of wire bond
interconnection
Table 1 lists the geometrical parameters, its description
and the range, they are allowed to vary in.

Parameter Description Ranges

Max. Loop
MH Height 100µm –300µm

S
Span of Loop 1mm – 3mm
Relative 1 (no Figure 2: Definition of design of experiment
εr Permittivity of encapsulation) –
encapsulation 3.5 Coupled Wire (Ball-Wedge)
According to the angle between the two adjacent wires,
DH Die Height 0 µm (recess) – the coupled wire bond simulations were divided into small
350µm angle (angle less than 20 degrees) and large angle (angles of
Electric Loss 45°, 90°, 135° and 180°) coupling simulations.
Tanδ Tangent of up to 0.01
encapsulation Case 1 – Small Angle (Ball-Wedge)
Table 1: Typical RF relevant parameter of single wire bond The main independent parameters for the small angle case
interconnection are the pitch of the wires on the die side (CH_PP), the angle
between the two wires (alpha) and the spans of the two wires
Furthermore, a two-level full factorial design with center (Loop A, Loop B).
point was chosen for the wire bonds. For each parameter, two Figure 3 illustrates the parameters of a coupled ball-wedge
levels within the range interval (see Table 2) were selected wire bond.
and combined with each other.
Since the glob top affects the capacitive coupling between
Figure 2 gives an idea how the design space appears the two wires, it is also included in the DOE definition as
geometrically for the inductance L, which depends on MH, S critical parameter.
and DH. The star markers (green) represent all combinations
of the chosen levels (Num_Levels Num_Parameters = 23 = 8) and
form one part of the design space (green box). The dot Loop A
marker (blue) is the center point and lies in the geometrical Chip Loop B
middle of the lower and upper range limit. Port 3 Port 2
Now, to enlarge the design space, two additional levels CH _PP
(the upper and lower range limit) for each parameter were
chosen and combined with the corresponding values of the
center point. They are represented by the rhomb markers
(red) and form the outer sphere of the design space.
Figure 2 on the whole shows very demonstratively the Port 4
geometry space, which closely related to a parameterized
function. Each of the markers describes the geometry for one Port 1
simulation. In fact, the parameterized function for the single Substrate
wire bond was based on 8+1+6 = 15 combinations
(simulation runs). Substrate

Figure 3: Critical design parameters for coupled ball-wedge

wire bonds (small angle)

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Case 2 – Large Angle (Ball-Wedge)
Large angle simulation includes the cases in which the
angle between two adjacent wires is larger than 45°.
Simulation points were chosen to investigate and extrapolate
the coupling terms from the small angle arrangement. The
main independent parameters are the pitch of the two wires on
the die side (CH_PP), the angle between the two wires (sites)
and the spans of the two wires (Loop A, Loop B).

Parameter Description Ranges

Sa Span of 0.75 mm – 2 mm
Loop a
Sb Span of 0.75 mm – 2 mm Figure 4: Cross-section of wire bond between die and
Loop b substrate, loop form
Relative 1 (without
εr Permittivity of encapsulation) – Main parasitic characteristic of wire bond is inductance,
encapsulation 3.5 as it is shown in Figure 9 with frequency dependent
α Angle between 0° - 180° magnitude of transmission coefficient. With increasing of
wire a and b span inductance increases as well. Second order geometry
Tanδ Electric Loss parameters are loop height and die height. The encapsulation
Tangent of up to 0.01 material influences capacitance of wire to ground.
encapsulation
CH_PP Die Pad Pitch 75µm – 300µm port1
Table 2: Typical RF relevant parameter of coupled wire bond
interconnection
Table 2 shows the varied parameter for both, the coupled
small angle and the coupled large angle wire bonds with port2
respective ranges. Again, a full factorial design with center
points was chosen for small angle coupled wire bond
simulation. Figure 5: EM simulation model, loop form
3D FEM Simulation
De-embedding
Ansoft High Frequency Structure Simulator (HFSS), using
finite element method, was employed to obtain the full wave The goal of de-embedding is to obtain RF interconnect
characteristics of wire bonds. Since the full wave simulator model without the pad parasitics. This leads to an
requires a uniform traveling wave to obtain the scattering interconnect model independent from chip and substrate
parameters (S-parameters) of the physical structures, a section technology. EM simulation and RF measurement takes place
of well developed transmission line section was added to each for the whole structure including feeding pads. Subtraction of
port. The effect of these transmission line feeds can be later pad parasitic can be carried out as explained in Figure 6.
removed from the total effects.
The electrical modeling of the wire bonds is based on Deembedding of the Wire from Pad
electromagnetic simulation results. Numerical simulation is
able to capture more physical configurations than assembly
Other advantages include less sample preparation times,
quicker to obtain results. It is, however, necessary to e γ l - Deembedding
experimentally validate the simulation-based parameterized
models.
ne of challenges was to generate a relevant loop form. e γ l - Deembedding
With definition of Span, Loop height and Die height the loop
and the effective line length is defined (see Figure 1). By
conducting a detailed analysis of bonding machine fabricated Square Pads: Chip = 125 x 125 µm
loop forms, a macro for automated wire bond model Substrate = 225 x 225 µm

generation was developed. Figure 5 shows a three [Y deemb ]= [Y Wire and Square Pads ]− [Y OPEN Square Pads ]
dimensional loop form in Ansoft’s HFSS simulation. A
geometrical analysis illustrates very good agreement between Figure 6: De-embedding of wire bond from pads
the assembled wire bond and the geometrical model (Figure 4
and Figure 5).

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 SimulateEntire Simulate
Structure without Wire(s)

De-embedded Up to De-embedded Up to
the Square Pads the Square Pads

Convert from Convert from

S to Y Spad to Ypad

Figure 8: The compact model for single wire bond: a)

Y-Ypad inductance only, b) unsymmetrical T model, c) symmetrical T
model

In the frequency range of interest, 1 GHz to 10 GHz, the

Convert resistance varies drastically due to the skin depth. And, the L
back to S and C are remained relatively unchanged.
Figure 10 shows the dependency of the inductance from
Figure 7: An HFSS Simulation for coupled wire bonds geometrical parameters. The main impact of course comes
from the span S of the wire and in second order from loop
In coupled wire bond simulation, Figure 3, the four ports height MH and die height DH. With increasing of MH and
were located on four separated planes to avoid the wave DH the loop length increases, therefor the inductance value
coupling between the feeds. In Figure 7, the procedure to enlarges as well.
obtain wire(s) only physical characteristics (S-parameters) is
illustrated. Please note that the “without wire(s)” simulation
has the identical fundamental structures as that of “Entire”
structure. That is, the feed structures in the two simulations
are remained the same. De-embedding of coupled wire bonds
needs considering of coupled pad parasitics.
The final S-parameters were expressed in the so-called
“touchstone” format. The format can be universally accepted
by other simulation and modeling platforms.
Model Extraction Using Optimization
Compact model extraction takes place. At first a compact
model structure which is able to describe wire bond
characteristic in needed frequency range and in full design
space. Compact modeling leads to an approximation of signal
behavior. With the number of elements the usable frequency
range is limited.
Optimization tool (Serenade Ansoft) was used to obtain
the compact models for R, L, and C using the touchstone S- G oal:EM -Sim ulation L-M odel
Sym m etricalT -M odel Unsym m etricalT -M odel
parameters obtained.
Figure 9: Compact model approximation of 3D full wave
Single Wire Bond calculation, comparison of different compact model structures
The following modeling structures shown in Figure 8 were
investigated: single inductance, unsymmetrical T model and
symmetrical T model.
Figure 9 shows the comparison of compact model
approximation for the 3 different models. Modeling of wire
with inductance only and unsymmetrical T model shows
agreement with 3D EM simulation up to frequency of about
3GHz. Better performance provides the symmetrical T model
(see Figure 8). The wire with typical span can be modeled up
to 10GHz.

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 0.50
Single W ire
3

2.5

Mutual Inductance in
Span = 2000µm
Span = 750µm
2
L_W ire in nH

0.25

1.5 M H=250,DH=262.5
M H=200,DH=175
M H=150,DH=262.5
1
M H=250,DH=87.5

M H=150,DH=87.5
0.5
0 0.5 1 1.5 2 2.5 3 3.5 0.00
S in mm 0 30 60 90
A ngelin °
Figure 10: Inductance of wire as function of loop span, loop
Figure 12: Mutual inductance as a function of angle between
height and die height
the wires and the span after compact modeling
Coupled Wire Bonds
Pitch Angle Span a Span b Coupling
Figure 11 shows the compact model for coupled wire in µm in mm in mm at 1GHz / dB
bonds. The schematic consists of two symmetrical T models 300 0 0.75 0.75 -31
and mutual inductance M12 and coupling capacitance CC 300 20 0.75 0.75 -33
between. It could be shown that for the transmission paths 300 45 0.75 0.75 -35
between ports 1 and 4 and/or ports 2 and 3, the results of 300 90 0.75 0.75 -38
300 135 0.75 0.75 -46
single wire modeling can be used. Moreover, this modeling 300 180 0.75 0.75 -65
procedure gives the opportunity to use the single wire results 300 0 2 2 -26
and switch on or off the coupling elements, dependent from 300 20 2 2 -31
application requirements. This model describes the 300 45 2 2 -35
electromagnetic simulation results in defined design space up 300 90 2 2 -41
300 135 2 2 -42
to 10 GHz with an error less than 1%. 300 180 2 2 -61
The dominant coupling effect is the mutual inductance Table 3: Coupling scattering parameter S13 as a function of
(Figure 12). Fore angle more than 90° the coupling reaches angle between the wires
values in order of – 40dB and below. In typical system
applications below – 40dB can be neglected (Table 3). These
values are very difficult to determine. Parameterization of Model
After the R, L, and C values of the single wire bond were
obtained for the entire DOE, as shown in Table 4, the R, L,
and C can be expressed as functions of the corresponding
independent factors (geometry parameters, see Table 1) by
applying appropriate optimization methods.
For the example of the single wire bond, following
functional dependencies are required:

C = f(MH,DH,S,εr)
L = f(MH,DH,S)
R = f(MH,DH,S)

The most important and challenging part of the

Figure 11: The Compact Model for Coupled Wire Bond
parameterization is the creation of a function model that
describes the physical impact of the geometry parameters in a
physically correct and mathematically effective way. Usually,
a polynomial approach is used. As an example, the
inductance, L, for a wire bond can be modeled as:
L ( MH , DH , S ) = a 0 + a 1 MH + a 2 DH + a 3 S + a 4 MH DH

+ a 5 MH S + a 6 DH S + a 7 MH DH S

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 The coefficients a0, a1,.... are calculated with help of the pads. During set-up the loop forming process was optimized
software JMP which uses the least square method to for each DOE type. Hysol FP4451 was dispensed as damming
determine coefficients of linear function models. JMP material and Hysol FP4450 for glob top and fully cured at
provides also statistical features, which allow the user to 150°C for 2 hours.
verify and validate the obtained function.
One of the critical criteria is to maximize the correlation
coefficient, Rsquare, which reflects the correlation between
the simulation (or measurement) results and the predicted
results using the parameterized function (model). The closer
the Rsquare to 1 the better the correlation between Lsimulated
and Lpredicted the better the prediction capability of the model.
After the parameterized models are validated, they will be
ported to a design system.
Experimental Validation
The E63E-A3 85% BiCMOS test die and LTCC test
substrate were used to obtain the electrical characteristics of
chip to substrate wire bond interconnects.
E63E Test Die
To characterize the wire bond interconnects test chips
were fabricated on E63E-A3 using 85% BiCMOS technology
by MOS16. Die A has both wire bond and flip chip test
structures, Die B and C are for wire bond characterization Figure 14: Die bond test chip on LTCC
only. Wire bond pads on die A are 70 µm wide 100 µm long
on 150 µm pitch. On die B the pads are 50 µm wide 70 µm Finally, all test vehicles were investigated by ultrasonic
long on 75 µm pitch. Die C has pads of 70 µm length with microscopy to ensure the completed flow of the epoxy resin.
variable widths. X-ray inspection from top and from the side was used to
measure the wire bond loop after completing the assembly
process.

Figure 15: X-ray inspection of test vehicle

Reverse engineering by cross-sectioning and metallurgical

Figure 13: E63E-A3 Test Chips (A, B, and C)
LTCC Test Substrate
LTCC test substrates were fabricated using both Dupont
951 and T2000 (Motorola IP) green tapes including wire
bond, flip chip and ceramic test structures. The top layer
metal can be either Au, Ag, or AgPd.
Fabrication of Test Vehicle
Die bonding was performed with a pick & place device
using a silver filled epoxy Ablebond 8360. The chips were
placed with an accuracy of less than 10 µm relative to the
chip and substrate pad positions. The adhesive was precured
at 110°C for 30 minutes to minimize bleeding of adhesive
(Figure 14). Final curing took place at 175°C for 1 hour. A
ball-wedge wire bonder and gold wire of 25 µm diameter was
used to connect the die pads with the corresponding substrate
analysis was performed for some electrically investigated test
vehicles to compare the actual geometry with the DOE
definitions (Figure 15).
Test Design – Principle of Measurement
Error! Reference source not found. shows the
measurement principle. The test chip is wire bonded on both
sides of the transmission line. On substrate side, wires are
bonded on vias to contact bottom substrate side. The whole
structure is under glob top so that measurement to extract the
influence of the glob top material is only possible from
backside. Assuming both wires are equal, additional
measurements are necessary to characterize vias, transmission
line and wires separately.
Full two port scattering parameter measurements were
carried out with vector network analyzer HP8510B in a
frequency range from 45 MHz to 26GHz. Measurement setup
includes a probe station with two coplanar microwave probes
connected to the test ports of HP8510B.

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 prime example, is described. Full wave simulator, the
Ansoft’s HFSS, was used to obtain the electrical
characteristics of the RF interconnect. Optimization was
then used to extract the R, L, and C for the wire bonds.
Parameterized electrical models of chip-to-substrate wire
bond interconnect were obtained using JMP, a statistics
tool. The test vehicle used to validate
the simulation results, were also designed and shown.
The validation results were reported. A very good
agreement (less than ±10%) between parameterized model
and measured inductance was achieved.
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0-7803-7038-4/01/$10.00 (C)2001 IEEE 2001 Electronic Components and Technology Conference