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Table Of Contents

Table 1. Revision History of this Document
Overview
ARCHITECTURE
Figure 1.Z80 CPU Block Diagram
CPU Registers
Figure 2.Z80 CPU Register Configuration
Arithmetic Logic Unit (ALU)
Instruction Register and CPU Control
PIN DESCRIPTION
Figure 3.Z80 I/O Pin Configuration
Pin Functions
Interrupt Request/Acknowledge Cycle
Figure 9.Interrupt Request/Acknowledge Cycle
Non-Maskable Interrupt Response
Figure 10.Non-Maskable Interrupt Request Operation
HALT Exit
Figure 11.HALT Exit
Power-Down Acknowledge Cycle
Power-Down Release Cycle
Figure 13.Power-Down Release Cycle No. 1
INTERRUPT RESPONSE
Interrupt Enable/Disable
Table 2. Interrupt Enable/Disable, Flip-Flops
CPU Response
Figure 16.Mode 2 Interrupt Response Mode
Interfacing Dynamic Memories
SOFTWARE IMPLEMENTATION EXAMPLES
Overview of Software Features
Examples of Specific Z80 Instructions
Figure 22.Shifting of BCD Digits/Bytes
Examples of Programming Tasks
Table 3. Bubble Listing
Z80 CPU Instruction Description
Instruction Types
Addressing Modes
Instruction Op Codes
Table 6. 8-Bit Load Group LD
Table 7. 16-Bit Load Group LD, PUSH and POP
Table 8. Exchanges EX and EXX
Table 9. Block Transfer Group
Table 10. Block Search Group
Table 11. 8-Bit Arithmetic and Logic
Table 12. General-Purpose AF Operation
Table 13. 16-Bit Arithmetic
Table 14. Rotates and Shifts
Table 15. Bit Manipulation Group
Table 18. Input Group
Table 19. 8-Bit Arithmetic and Logic
Table 20. Miscellaneous CPU Control
Z80 Instruction Set
Z80 Assembly Language
Z80 Status Indicator Flags
Add/Subtract Flag
Z80 Instruction Description
8-Bit Load Group
LD r, r'
LD (IX+d), r
LD (IY+d), r
LD (HL), n
LD (IX+d), n
LD (IY+d), n
LD A, (BC)
LD A, (DE)
LD A, (nn)
LD (BC), A
LD (DE), A
LD (nn), A
LD A, I
LD A, R
LD I,A
LD R, A
16-Bit Load Group
LD dd, nn
LD IX, nn
LD IY, nn
LD HL, (nn)
LD dd, (nn)
LD IX, (nn)
LD IY, (nn)
LD (nn), HL
LD (nn), dd
LD (nn), IX
LD (nn), IY
LD SP, HL
LD SP, IX
LD SP, IY
PUSH qq
PUSH IX
PUSH IY
POP qq
POP IX
POP IY
Exchange, Block Transfer, and Search Group
EX DE, HL
EX AF, AF'
EX (SP), HL
EX (SP), IX
EX (SP), IY
LDIR
LDDR
CPIR
CPDR
8-Bit Arithmetic Group
ADD A, r
ADD A, n
ADD A, (HL)
ADD A, (IX + d)
ADD A, (IY + d)
ADC A, s
SUB s
SUB r
SUB n
SBC A, s
SBC A, r
SBC A, n
OR s
XOR s
CP s
INC r
INC (HL)
INC (IX+d)
INC (IY+d)
DEC m
General-Purpose Arithmetic and CPU Control Groups
HALT
DI
EI
IM 0
IM 1
IM 2
16-Bit Arithmetic Group
ADD HL, ss
ADC HL, ss
SBC HL, ss
ADD IX, pp
ADD IY, rr
INC ss
INC IX
INC IY
DEC ss
DEC IX
DEC IY
Rotate and Shift Group
RLCA
RRCA
RLC r
RLC (HL)
RLC (IX+d)
RLC (IY+d)
RL m
RRC m
RR m
SLA m
SRA m
SRL m
Bit Set, Reset, and Test Group
BIT b, r
BIT b, (HL)
BIT b, (IX+d)
BIT b, (IY+d)
SET b, r
SET b, (HL)
SET b, (IX+d)
SET b, (IY+d)
RES b, m
RES b, rn
Jump Group
JP nn
JP cc, nn
JR NC, e
JR Z, e
JR NZ, e
JP (HL)
JP (IX)
JP (IY)
DJNZ, e
Call And Return Group
CALL nn
CALL cc, nn
RET cc
RETI
RETN
RST p
Input and Output Group
IN A, (n)
IN r (C)
INIR
INDR
OUT (n), A
OUT (C), r
OUTI
OTIR
OUTD
OTDR
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