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Table Of Contents

1.1OVERVIEW
1.2LITERATURE SURVEY
1.3OBJECTIVE OF THESIS
2.1 INTRODUCTION
2.2 ERROR DETECTION AND ERROR CORRECTION
2.3.1 TERMINOLOGIES AND DEFINITIONS USED IN EDAC CODES
2.3.2.1 Parity Codes
2.3.2.2 Checksum Codes
2.3.2.3 m-out-of-n Codes
2.3.2.4 Berger Codes
2.3.3.1 Bose – Chaudhuri – Hocquenqhem (BCH) Codes
2.3.3.2 Hamming Single Error – Correcting Codes
3.1 INTRODUCTION
3.2 DEFINITION OF GALOIS FIELD
3.3 PROPERTIES OF GALOIS FIELDS
3.4 CONSTRUCTION OF GALOIS FIELDS
3.5 GALOIS FIELD ARITHMETIC
4.1 INTRODUCTION
4.2 RS CODES BACKGROUND
4.3Characteristics of the RS Encoder
4.4 DESIGN AND IMPLEMENTATION
4.5 SELF-CHECKING RS ENCODER
4.6 CONCURRENT ERROR DETECTION SCHEME OF THE RS DECODER
5.1 History of FPGA
5.3 FPGA Advantage
5.4 Language Used in FPGA
5.5 Importance of HDLs
6.1 Introduction
6.2 Behavioral level
6.3 Register-Transfer Level
6.4 Gate Level
6.5 History of Verilog
6.6 Features of Verilog HDL
6.7 Simulation
6.8 SYNTHESIS:
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Reed Solomon Doc

Reed Solomon Doc

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Published by: kalkam on Dec 15, 2010
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11/19/2012

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