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ASIC Design: CMOS Logic Latches

ASIC Design: CMOS Logic Latches

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This paper answers questions about the design and physical CMOS layout of electronic logic latches. It clearly indicates their operation using block diagrams and related functions, and demonstrates functionality in gate & transistor schematics and physical level layouts.
This paper answers questions about the design and physical CMOS layout of electronic logic latches. It clearly indicates their operation using block diagrams and related functions, and demonstrates functionality in gate & transistor schematics and physical level layouts.

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Published by: Muhammad Fahd Waseem on Dec 22, 2010
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GIKI INTERNAL COMPILATION FOR
CS465
ASIC DESIGN PROJECTS 1
Discussion and CMOS Design of Logic Latches
Muhammad Fahd Waseem,
Member, IEEE 
 Abstract
—This assignment answers questions about the designand physical CMOS layout of electronic logic latches. It clearlyindicates their operation using block diagrams and relatedfunctions, and demonstrates functionality in gate & transistorschematics and physical level layouts.
 Note that flip-flops are expressly removed from this paper, as they are non-transparent, while latches are transparent. Index Terms
—Latches, Flip-Flops, ASIC, VLSI, MicroWind,Switch Level, Physical Level
I. I
NTRODUCTION
I
N electronics, a latch is a kind of bistable multivibrator, anelectronic circuit that has two stable states and therefore canstore one bit of information. Today the word is mainly usedfor simple transparent storage elements, while slightly moreadvanced non-transparent (or clocked) devices are describedas flip-flops.While gates have to be built directly from transistors, latchescan be built from gates, and flip-flops can be built from latches.Both latches and flip-flops are circuit elements whose outputdepends not only on the current inputs, but also on previousinputs and outputs. The difference between a latch and a flip-flop is that a latch does not have a clock signal, whereas aflip-flop always does [1]. Generally defined, a clock is an edgetriggering mechanism, while an enable (or a gate) is a leveltriggering mechanism.In other words, a true latch is always
asynchronous
whilea flip-flop is always
synchronous
. Because the distinctionbetween a flip-flop and a latch is clear, this paper will adhereto the correct technical definitions as per the title, and describeproper latches only.Latches may be
gated 
, or
non-gated 
, depending on whetherthey have an
enable
input.II. L
ATCH
T
YPES
 A. SR Latches
When using static gates as building blocks, the most fun-damental latch is the simple SR latch, where S and R standfor
set 
and
reset 
. It can be constructed from a pair of cross-coupled logic gates. The stored bit is present on the outputmarked Q. See Fig. 1 & 2.Normally, in storage mode, the S and R inputs are both low,and feedback maintains the Q and Q outputs in a constantstate, with Q the complement of Q. If S is pulsed high whileR is held low, then the Q output is forced high, and stays highwhen S returns to low; similarly, if R is pulsed high while S
This is NOT a research paper, though every attempt has been made tokeep the information in this document as accurate as possible. This paper isreleased under the Creative Commons Share-Alike license only.This paper has been typeset in L
A
TEX2
ε
, using the standard IEEEtran classin
two-sided, Journal paper 
mode and A4 page sizing.
Fig. 1: (a) SR Latch, and (b) D LatchFig. 2: Blocks for (a) SR Latch, and (b) D Latchis held low, then the Q output is forced low, and stays lowwhen R returns to low. See Table I.The NOR gates in the SR latch can also be replaced byNAND gates, to gain an SR latch i.e. an SR latch with activelow inputs.
 B. Sub latch types based on the SR Latch
The R = S = 1 combination is called a restricted combi-nation or a forbidden state because, as both NOR gates thenoutput zeros, it breaks the logical equation Q =
not 
Q. Thecombination is also inappropriate in circuits where both inputsmay go low simultaneously (i.e. a transition from restrictedto keep). The output would lock at either 1 or 0 dependingon the propagation time relations between the gates (a racecondition). In certain implementations, it could also lead tolonger ringings (damped oscillations) before the output settles,and thereby result in undetermined values (errors) in high-frequency digital circuits. Although this condition is usuallyavoided, it can be useful in some applications.To overcome the restricted combination, one can add gatesto the inputs that would convert (S,R) = (1,1) to one of thenon-restricted combinations. That can be:
Q = 1 (1,0) – referred to as an S-latch
Q = 0 (0,1) – referred to as an R-latch
Keep state (0,0) – referred to as an E-latch
Toggle the output – referred to as a JK-latchTABLE I: State Table for SR Latch
S R Output
0 0 Keep State0 1 Q=01 0 Q=11 1 Restricted Combination
 
2 GIKI INTERNAL COMPILATION FOR
CS465
ASIC DESIGN PROJECTS
TABLE II: State Table for D Latch
D Output
1 Q=10 Q=0
Fig. 3: Gated, (a) SR Latch, and (b) D Latch
C. D Latches
This latch exploits the fact that in the two active inputcombinations (01 and 10) of the SR latch, R is the complementof S. The NOT gate converts the two D input states (0 and1) to these two input combinations for the SR latch. Thus aD-latch may be considered as a one-input asynchronous SRlatch. This configuration prevents from applying the restrictedcombination to the inputs. It is also known as transparent latch,or data latch. The word transparent comes from the fact thatthe signal propagates directly through the circuit, from theinput D to the output Q. See Fig. 1 & 2 and Table II.Transparent latches are typically used as I/O ports or inasynchronous systems. They are available as integrated cir-cuits, usually with multiple latches per circuit.
 D. Gated SR Latch
A gated SR latch can be made by adding a second levelof NAND gates to the inverted SR latch (or a second levelof AND gates to the direct SR latch). The extra gates furtherinvert the inputs so the simple SR latch becomes a gated SRlatch (and a simple SR latch would transform into a gated SRlatch with inverted enable). See Fig. 3 & 4.With E high (enable true), the signals can pass through theinput gates to the encapsulated latch; all signal combinationsexcept for (0,0) =
hold 
then immediately reproduce on the(Q,Q) output, i.e. the latch is transparent.With E low (enable false) the latch is closed (opaque) andremains in the state it was left the last time E was high. SeeTable III.Fig. 4: Blocks for Gated (a) SR Latch, and (b) D LatchTABLE III: State Table for Gated SR and D Latches
E/C State
0 No Change / Keep State1 Same as Regular Latch
 E. Gated D Latches
The gated D latch works in the same way as the D latchwith the SR latch. The two non-gate inputs to the gated SRlatch are bound by a NOT gate. With E low (enable false) thelatch is closed (opaque) and remains in the state it was leftthe last time E was high. See Fig. 3 & 4 and Table III. Thereare no invalid states.III. S
PECIFICATIONS
We are required to design optimized D latches as defined by the project guidelines for the CS465 Asic Design course project [2].
These requirements are drawn from the coursetextbook (Introduction to VLSI Circuits and Systems, by JohnP. Uyemura).Standard design rules and methodologies must be appliedto design the stated latches. Verilog must be used as the HDL,block diagrams must be displayed and simulations must all becomplete.IV. D
ESIGN
M
ETHODOLOGY
It is our requirement to design for, and test, the givenobjectives, but not produce fabricatable packages. So ourdesign methodology shall follow the standard CMOS-VLSIdesign flow for digital circuits,1) System Specification: What is the application / systemwe need to design, and with what parameters.2) System Design and Verification: To be done on a highlevel schematic simulator, Verilog HDL (behavioral),or an equivalent high level model extractor. For lesscomplicated specifications, this step may be skipped.3) Logic Synthesis: Reducing the system design to gatelevel descriptions, and subsequent verification. This usu-ally entails a simulation or test in Verilog at the gate / RTL level, or a dedicated logic level simulator.4) Circuit Design: For CMOS design, this entails reducingthe gate level design into an optimized transistor levelcircuit, and subsequent testing.5) Physical Design: The circuit design is converted intooptimized silicon layouts. Layouts at this level aregenerally optimized according to a set of design rules,and tested using extended SPICE models.V. D
ESIGN
E
NVIRONMENT
The design environment is defined as the ecosystem of software tools and kits available during the design phase of the project [3].
 A. Software Tools
GNU CC: The GNU C Compiler. Used in a Linuxenvironment for testing SystemC code.
ModelSim™: The industry standard HDL & system levelsynthesis and simulation suite.
DSCH: A digital schematic editor and simulator, writtenfor academic purposes by Dr. Etienne Sicard, based inToulouse, France [4].
µ
Wind (MicroWind): A physical layout design tool andsimulator for CMOS circuits, also written by Dr. EtienneSicard.
 
M.F. WASEEM, M.D. ZARRAR, AND I. AZIZ: DISCUSSION AND CMOS DESIGN OF LOGIC LATCHES 3
 B. BSIM4: Berkeley MOSFET SPICE Simulato
MicroWind integrates BSIM4 (Berkeley MOSFET SPICESimulator) into the simulations it performs.BSIM4, as an extension of BSIM model, addresses theMOSFET physical effects into sub-100nm regime. It isa physics-based, accurate, scalable, robustic and predictiveMOSFET SPICE model for circuit simulation and CMOStechnology development. It is developed by the BSIM Re-search Group in the Department of Electrical Engineering andComputer Sciences (EECS) at the University of California,Berkeley. BSIM is charted by the Compact Model Council(CMC) [5]. It is a consortium of semiconductor companiesand simulator vendors world-wide promoting BSIM3v3 devel-opment as the industry standard compact model. The councilis affiliated with Electronic Industries Alliance (EIA).BSIM4 is handled from within the MicroWind interfaceusing a series of parameters. As such, it is among the mostaccurate SPICE simulators for CMOS available in the market.While commercial EDA tool vendors have models furtheradvanced in accuracy, BSIM4 is perfectly sufficient for ourrequirements.
C. Restrictions of the Used Software Tools
Our selection of software tools imposes some restrictionsof the kind of design that can be implemented.ModelSim is the least restricting of those, because of itspervasive commercial background. Its standard method forHDL simulations is a slightly old technique, whereby thetestbench must be created from HDL itself.DSCH and MicroWind suffer from a limit on the size of thenetlist. Extremely large circuits cannot be simulated on them.The macros for collective operations are poor: undo is limitedto one operation, collective resizing does not follow polygonrules, attributes cannot be changed by multiple selection, andso on. Moreover, DSCH tends to fixate the orientation of the symbols for transistors, making the re-orienting of theseparticularly painstaking.MicroWind also does not support cell methods. This maybe a major problem when designing large circuits that rely onmultiple repeating units.Despite these restrictions, the design environment is suffi-cient for our requirements. Our specifications do not call forlarge complex designs, but highly optimized small designs. Wedo not require the use of cells in our design, and by issuingsoftware commands carefully (and taking repeated backups),we can avoid the pitfalls of the lack of GUI macros in DSCHand MicroWind.VI. H
IGH
L
EVEL
B
EHAVIORAL
M
ODELING IN
S
YSTEM
CSystemC is a language built in C++ that spans from con-cept to implementation in hardware and software. The IEEEStandards Association approved the standard for the SystemClibrary as IEEE Std. 1666™ 2005 [6].We used SystemC to design a basic D latch, just to testthe highest level of abstraction available. The advantage of using SystemC lay in the true high-level abstraction it offers,as opposed to the pseudo behavioral abstraction offered byVerilog in the
always
blocks it uses.Appendix A shows the code we used to implement the latch.The text results immediately follow it. It may be noted that thetesting was extremely rudimentary, and not very exhaustive ineither scope or optimization. The purpose was just to get ataste of the language. In our case, the Mint 6 distribution of Linux was used for the compilation.VII. N
OTES ON THE
L
AYOUTS
I
MPLEMENTED
Throughout our layout designs, it should be noted that weimplemented our design rules based on the
CMOS 90nm,6 Metal Copper, Strained SiGe Low
fabrication process.For this process, some of the design rules pertinent to ourrequirements are given in Appendix B. It may be noted thatthe design rules file specifies many other rules, and manyspecifications for use by the SPICE engine in MicroWind, butto specify them here is beyond the scope of this paper.We used
λ
design rules, with
1
λ
= 0
.
050
µ
m.
2
λ
is thesmallest possible channel length, according to the design rules.Electrical symmetry was maintained wherever possible. Wedecided to use a baseline NFET size, and then resize thePFETs accordingly to achieve the symmetry. The aspect ratioof the baseline NFET was chosen to be 5, i.e.
10
λ/
2
λ
dueto the channel length sizing restriction. The channel length isalways kept at
λ
= 2
, for both PFETs and NFETs. In resizing,only the channel width was changed for the PFETs.The mobility ratio
r
(of P-channel FETs to N-channel FETs)depends on the manufacturing process. However, it is rarethat exact mobilities are provided. In that case, it is possibleto use the I
DS
to V
DS
curves of tranistors to find
r
becausemobility
(
µ
)
(current carried). So,
r
=
µ
N
µ
P
=
I
DS, N
I
DS, P
All other variables constant
To process the given equation, we generated I–V curves forone NFET and one PFET, with channel dimensions for bothbeing sized at
10
λ
×
2
λ
. The curves are shown in Fig. 5.Choosing the values for V
DS
=
V
GS
=
±
1
.
20
V, we find,
r
=
I
DS, N
I
DS, P
650
µ
A
350
µ
A
= 1
.
86
1
.
86
= 2
Thus, we shall use the value of 
r
= 2
where needed.The unusual shapes and sizes of interlayer contacts willbe noted: these are to optimize contact resistances whilecomplying with the design rules. These lead to higher signalfidelity.The physical layouts were almost entirely made in levelsMetal 1 and below. Only in the case of a capacitance require-ment were we forced to move to Metal 2. N-wells were allrooted to the highest potential, and the substrate was groundedto the lowest potential in all cases.Circuit setup times in the SPICE / BSIM4 / MicroWindsimulations were ignored - these are typically within the first200ps.For logic values, V
DD
was considered 1.20V and V
SS
0.00V.The colour and sketchmark legend given in Fig. 6 isfollowed throughout this paper for physical CMOS layouts.

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