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Table Of Contents

Summary: History of VHDL
Levels of Abstraction
Levels of abstraction in the context of their time domain
Algorithm
RTL
Gates
Writing VHDL for Synthesis
Scope of VHDL
System level
Digital
Analogue
Design process
Design Flow using VHDL
System-level Verification
RTL design and test bench creation
RTL verification
Look-ahead Synthesis
Benefits of using VHDL
Executable specification
S.NO COMPONENT QUANTITY
SOFTWARE USED: Quartus-II
AND gate
OR gate
NOT gate
NAND gate
NOR gate
EXOR gate
EXNOR gate
Table 1: Logic gates representation using the Truth table
ALL GATES Output Equations:
VHDL CODE:
EXPECTED RESULTS (HARDWARE):
AND GATE OR GATE
NAND GATE NOR GATE
EX-OR GATE EX-NOR GATE
EXPECTED RESULTS (SOFTWARE):
Fig: Simulation Report of ALL GATES
RESULTS (HARDWARE):
AND GATE OR GATE
NAND GATE NOR GATE
EX-OR GATE EX-NOR GATE
Fig: Simulation Results of ALL GATES
RESULT:
INFERENCE:
PRECAUTIONS (SOFTWARE):
PRECAUTIONS (HARDWARE):
QUESTIONS & ANSWERS:
PROCEDURE (HARDWARE):
SOFTWARE USED: Quartus-II THEORY:
D-FLIP FLOP DETAILS:
INTERNAL DIAGRAM:
D FLIP- FLOP Output Equations:
RESULTS (SOFTWARE): Fig: Simulation Report of D FLIP- FLOP RESULTS (HARDWARE):
PROCEDURE (SOFTWARE):
APPARATUS: HARDWARE:
SOFTWARE: Quartus-II THEORY:
TRUTH TABLE: COUNT OUTPUT
QD QC QB QA
Decade Counter Output Equations:
Reset inputs Output
RESULTS (SOFTWARE):
Fig: Simulation Report of Decade Counter
COUNT OUTPUT
S.NO COMPONENTQUANTITY
THEORY:
4 BIT COUNTER DETAILS:
PIN DIAGRAM:
TRUTH TABLE:
Fig: Simulation Report of Four Bit Counter
THEORY (HARDWARE):
SHIFT REGISTER DETAILS:
TRUTH TABLE: INPUTS OUTPUTS
UNIVERSAL SHIFT REGISTER OUTPUT EQUATIONS:
Fig: Simulation Report of Shift Register
Fig: Compilation Report of Universal Shift Register
DECODER DETAILS:
3- 8 Decoder Output Equations:
INPUTS OUTPUTS
Fig: Simulation Report of 3-to-8 DECODER
APPARATUS:
FOUR BIT COMPARATOR DETAILS:
COMPARING INPUTS CASCADING
FOUR BIT COMPARATOR OUTPUT EQUATIONS:
Fig: Simulation Report of 4 bit Comparator
Fig: Simulation Results of 4 bit Comparator
OUTPUT EQUATIONS:
INPUT OUTPUT
Fig: Simulation Results of 8X1 MULTIPLEXER
2X4 DEMULTIPLEXER DETAILS: TRUTH TABLE:
Fig: Simulation Report of 2X4 DEMULTIPLEXER
RAM OUTPUT EQUATIONS:
INPUT OPERATION CONDITION OF OUTPUT
Fig: Compilation Report of RAM (16x4)
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Finale Cad Lab Manual

Finale Cad Lab Manual

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Published by: kandulakm on Jan 05, 2011
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10/22/2012

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