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ƥ CPU must:
ƜFetch instructions
ƜInterpret instructions
ƜFetch data
ƜProcess data
ƜWrite data

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ƥ CPU must have some working space (temporary
storage)
ƥ Called registers
ƥ Number and function vary between processor
designs
ƥ One of the major design decisions
ƥ Top level of memory hierarchy
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ƥ General Purpose
ƥ Data
ƥ Address
ƥ Condition Codes
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ƥ May be true general purpose
ƥ May be restricted
ƥ May be used for data or addressing
ƥ Data
ƜAccumulator
ƥ Addressing
ƜSegment
'
  ¢  "#
ƥ Make them general purpose
ƜIncrease flexibility and programmer options
ƜIncrease instruction size & complexity
ƥ Make them specialized
ƜSmaller (faster) instructions
ƜLess flexibility
s$%'¢  &
ƥ Between 8 - 32
ƥ Fewer = more memory references
ƥ More does not reduce memory references and
takes up processor real estate
ƥ See also RISC
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ƥ Large enough to hold full address
ƥ Large enough to hold full word
ƥ Often possible to combine two data registers
ƜC programming
Ɯdouble int a;
Ɯlong int a;

  
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ƥ Sets of individual bits
Ɯe.g. result of last operation was zero
ƥ Can be read (implicitly) by programs
Ɯe.g. Jump if zero
ƥ Can not (usually) be set by programs


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ƥ Program Counter
ƥ Instruction Decoding Register
ƥ Memory Address Register
ƥ Memory Buffer Register

ƥ Revision: what do these all do?

 |
ƥ A set of bits
ƥ Includes Condition Codes
ƥ Sign of last result
ƥ Zero
ƥ Carry
ƥ Equal
ƥ Overflow
ƥ Interrupt enable/disable
ƥ Supervisor
 ( %
ƥ Intel ring zero
ƥ Kernel mode
ƥ Allows privileged instructions to execute
ƥ Used by operating system
ƥ Not available to user programs
¢ 
ƥ May have registers pointing to:
ƜProcess control blocks (see O/S)
ƜInterrupt Vectors (see O/S)

ƥ N.B. CPU design and operating system design

are closely linked
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ƥ Revision
ƥ Stallings Chapter 3
 


ƥ May require memory access to fetch operands
ƥ Indirect addressing requires more memory
accesses
ƥ Can be thought of as additional instruction
subcycle
   

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ƥ Depends on CPU design
ƥ In general:

ƥ Fetch
ƜPC contains address of next instruction
ƜAddress moved to MAR
ƜAddress placed on address bus
ƜControl unit requests memory read
ƜResult placed on data bus, copied to MBR, then to IR
ƜMeanwhile PC incremented by 1
*
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ƥ IR is examined
ƥ If indirect addressing, indirect cycle is
performed
ƜRight most N bits of MBR transferred to MAR
ƜControl unit requests memory read
ƜResult (address of operand) moved to MBR
*
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ƥ May take many forms
ƥ Depends on instruction being executed
ƥ May include
ƜMemory read/write
ƜInput/Output
ƜRegister transfers
ƜALU operations
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ƥ Simple
ƥ Predictable
ƥ Current PC saved to allow resumption after
interrupt
ƥ Contents of PC copied to MBR
ƥ Special memory location (e.g. stack pointer)
loaded to MAR
ƥ MBR written to memory
ƥ PC loaded with address of interrupt handling
routine
ƥ Next instruction (first of interrupt handler) can
be fetched
*
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+
ƥ Fetch accessing main memory
ƥ Execution usually does not access main memory
ƥ Can fetch next instruction during execution of
current instruction
ƥ Called instruction prefetch
(+
ƥ But not doubled:
ƜFetch usually shorter than execution
ƛ Prefetch more than one instruction?
ƜAny jump or branch means that prefetched
instructions are not the required instructions
ƥ Add more stages to improve performance
 
 
ƥ Fetch instruction
ƥ Decode instruction
ƥ Calculate operands (i.e. EAs)
ƥ Fetch operands
ƥ Execute instructions
ƥ Write result

ƥ Overlap these operations

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ƥ Multiple Streams
ƥ Prefetch Branch Target
ƥ Loop buffer
ƥ Branch prediction
ƥ Delayed branching
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ƥ Have two pipelines
ƥ Prefetch each branch into a separate pipeline
ƥ Use appropriate pipeline

ƥ Leads to bus & register contention

ƥ Multiple branches lead to further pipelines being
needed
+V
ƥ Target of branch is prefetched in addition to
instructions following branch
ƥ Keep target until branch is executed
ƥ Used by IBM 360/91
] ++
ƥ Very fast memory
ƥ Maintained by fetch stage of pipeline
ƥ Check buffer before fetching from memory
ƥ Very good for small loops or jumps
ƥ c.f. cache
ƥ Used by CRAY-1
] ++* 
  "#
ƥ Predict never taken
ƜAssume that jump will not happen
ƜAlways fetch next instruction
Ɯ68020 & VAX 11/780
ƜVAX will not prefetch after branch if a page fault
would result (O/S v CPU design)
ƥ Predict always taken
ƜAssume that jump will happen
ƜAlways fetch target instruction
  "#
ƥ Predict by Opcode
ƜSome instructions are more likely to result in a jump
than thers
ƜCan get up to 75% success
ƥ Taken/Not taken switch
ƜBased on previous history
ƜGood for loops
  ",#
ƥ Delayed Branch
ƜDo not take jump until you have to
ƜRearrange instructions
  
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  * 
*
| 


-./-0 
 
ƥ Fetch
Ɯ From cache or external memory
Ɯ Put in one of two 16-byte prefetch buffers
Ɯ Fill buffer with new data as soon as old data consumed
Ɯ Average 5 instructions fetched per load
Ɯ Independent of other stages to keep buffers full
ƥ Decode stage 1
Ɯ Opcode & address-mode info
Ɯ At most first 3 bytes of instruction
Ɯ Can direct D2 stage to get rest of instruction
ƥ Decode stage 2
Ɯ Expand opcode into control signals
Ɯ Computation of complex address modes
ƥ Execute
Ɯ ALU operations, cache access, register update
ƥ Writeback
Ɯ Update registers & flags
Ɯ Results sent to cache & bus interface write buffers
-./-0    
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%%1¢ % 
ƥ MMX uses several 64 bit data types
ƥ Use 3 bit register address fields
Ɯ8 registers
ƥ No MMX specific registers
ƜAliasing to lower 64 bits of existing floating point
registers
% +%%1¢  

 2 ¢ 
   
ƥ Interrupts
ƜMaskable
ƜNonmaskable
ƥ Exceptions
ƜProcessor detected
ƜProgrammed
ƥ Interrupt vector table
ƜEach interrupt type assigned a number
ƜIndex to vector table
Ɯ256 * 32 bit interrupt vectors
ƥ 5 priority classes
$
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ƥ Processor examples
ƥ Stallings Chapter 12
ƥ Manufacturer web sites & specs