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Table Of Contents

1−2: About Electric
1−3: Running Electric
1−4: Building Electric from Source Code
1−7: The Display
1−8: The Mouse
1−9: The Keyboard
1−10: IC Layout Tutorial
1−11: Schematics Tutorial
1−12: Schematics and Layout Tutorial
Chapter 2: Basic Editing
2−1: Selection
2−2: Circuit Creation
2−3: Circuit Deletion
2−4: Circuit Modification
2−5: Changing Size
2−6: Changing Orientation
Chapter 3: Hierarchy
3−1: Cells
3−2: Cell Creation and Deletion
3−3: Creating Instances
3−4: Examining Cell Instances
3−5: Moving Up and Down the Hierarchy
3−6: Exports
3−7: Cell Information
3−8: Rearranging Cell Hierarchy
3−9: Libraries
3−10: Copying Cells Between Libraries
3−11: Views
Chapter 4: Display
4−1: The Tool Bar
4−2: The Messages Window
4−3: Creating and Deleting Editing Windows
4−4: Zooming and Panning
4−5: The Sidebar
4−6: Color
4−7: Grids and Alignment
4−8: Printing
4−9: Text Windows
4−10: 3D Windows
4−11: Waveform Windows
Chapter 5: Arcs
5−1: Introduction to Arcs
5−2: Constraints
5−3: Setting Constraints
5−4: Other Properties
5−5: Default Arc Properties
Chapter 6: Advanced Editing
6−1: Making Copies
6−2: Creation Defaults
6−3: Preferences
6−4: Making Arrays
6−5: Spreading Circuitry
6−6: Replacing Circuitry
6−7: Undo Control
6−8: Text
6−9: Networks
6−10: Outlines
6−11: Interpretive Languages
6−12: Project Management
6−13: CVS Project Management
6−14: Emergencies
Chapter 7: Technologies
7−1: Introduction to Technologies
7−3: I/O Control
7−4: The MOS Technologies
7−5: Schematics
7−6: Special Technologies
Chapter 8: Creating New Technologies
8−1: Technology Editing
8−2: Converting between Technologies and Libraries
8−3: Hierarchies of Technology Libraries
8−4: The Layer Cells
8−5: The Arc Cells
8−6: The Node Cells
8−7: Miscellaneous Information
8−8: How Technology Changes Affect Existing Libraries
8−9: Examples of Use
8−10: Technology XML File Format
8−11: The Technology Creation Wizard
Chapter 9: Tools
9−1: Introduction To Tools
9−2: Design Rule Checking (DRC)
9−3: Electrical Rule Checking (ERC)
9−4: Simulation Interface
9−5: Simulation (built−in)
9−6: Routing
9−7: Network Consistency Checking (NCC)
9−8: Generation
9−9: Logical Effort
9−10: Extraction
9−11: Compaction
9−12: Silicon Compiler
9−13: Placement
Chapter 10: The JELIB and DELIB File Format
10−1: Introduction to File Format
10−2: Header
10−3: Body
10−4: Miscellaneous
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Electric v9.00 Manual

Electric v9.00 Manual

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Published by Chi_Ho_Wong

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Published by: Chi_Ho_Wong on Jan 06, 2011
Copyright:Attribution Non-commercial

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