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Table Of Contents

Operation: r, ← r'
Op Code: LD
Operands: r, r'
Register r, C
M Cycles T States MHz E.T
Condition Bits Affected: None
Operation: r ← n
Operands: r, n
M Cycles T States 4 MHz E.T
Operation: r ← (HL)
Operands: r, (HL)
Operation: r ← (IX+d)
Operands: r, (IX+d)
Operation: r ← (IY+D)
Operands: r, (lY+d)
Operation: (HL) ← r
Operands: (HL), r
Operation: (IX+d) ← r
Operands: (IX+d), r
Operation: (lY+d) ← r
Operands: (lY+d), r
Operation: (HL) ← n
Operands: (HL), n
Operation: (IX+d) ← n
Operands: (IX+d), n
Operation: (lY+d) ← n
Operands: (lY+d), n
Operation: A ← (BC)
Operands: A, (BC)
Operation: A ← (DE)
Operands: A, (DE)
Operation: A ← (nn)
Operands: A, (nn)
Operation: (BC) ← A
Operands: (BC), A
Operation: (DE) ← A
Operands: (DE), A
M cycles T States 4 MHz E.T
Operation: (nn) ← A
Operands: (nn), A
Operation: A ← 1
Operands: A, I
Operation: A, ← R
Operands: A, R
Operation: I ← A
Operands: I, A
Operation: R ← A
Operands: R, A
Operation: dd ← nn
Operands: dd, nn
Pair dd
Operands: dd, (nn)
Operands: IX, (nn)
Operands: IY, (nn)
Operands: (nn), IY
Operation: SP ← HL
Operands: SP, HL
Operation: SP ← - IX
Operands: SP, 1X
Operation: SP ← IY
Operands: SP, lY
Operands: qq
Pair qq
Operands: IX
Operands: IY
Pair r
Operands: lY
Operation: DE ↔ HL
Op Code: EX
Operands: DE, HL
Operation: AF ↔ AF'
Operands: AF, AF'
Op Code: EXX
Operands: —
Operands: (SP), HL
Operands: (SP), IX
Operands: (SP), IY
Op Code: LDI
Condition Bits Affected:
Op Code: LDIR
Operands: B8
Op Code: LDD
Op Code: LDDR
Op Code: CPI
Op Code: CPIR
Op Code: CPD
Op Code: CPDR
Operands: A, (HL)
Op Code: ADC
Operands: A, s
Operation: A ← A - s
Op Code: SUB
Operands: s
Op Code: SBC
InstructionM Cycles T States 4 MHz E.T
Operation: A ← A ∧ s
Op Code: AND
Operation: A ← A ∨ s
Op Code: OR
InstructionM cycles T States 4 MHz E.T
Operation: A ← A ⊕ s
Op Code: XOR
Operation: A - s
Op Code: CP
Operation: r ← r + 1
Operands: r
Operands: (HL)
Operands: (IX+d)
Operands: (lY+d)
Operation: m ← m- 1
Op Code: DEC
Operands: m
Operation:
Op Code: DAA
Operation: A ← A
Op Code: CPL
Operation: A ← 0 - A
Op Code: NEG
Operation: CY ← CY
Op Code: CCF
Operation: CY ← 1
Op Code: SCF
Op Code: NOP
Op Code: HALT
Operation: IFF ← 0
Op Code: DI
Operation: IFF ← 1
Op Code: EI
Operands: 0
Operands: 1
Operands: 2
Operation: HL ← HL + ss
Operands: HL, ss
Register Pair ss
Operation: IX ← IX + pp
Operands: IX, pp
Register Pair pp
Operation: IY ← IY + rr
Operands: IY, rr
Register Pair rr
Operation: ss ← ss + 1
Operands: ss
Operation: IX ← IX + 1
Operation: IY ← IY + 1
Operation: ss ← ss - 1
Operation: IX ← IX - 1
Operation: IY ← IY - 1
Op Code: RLCA
Op Code: RLA
Condition Bits Affected: Condition Bits Affected
Op Code: RRCA
Op Code: RRA
Op Code: RLC
Op Code: PL
Op Code: RRC
Op Code: RR
Op Code: SLA
Op Code: SRA
Op Code: SRL
Op Code: RLD
Op Code: RRD
Operation: Z ← rb
Op Code: BIT
Operands: b, r
Bit Tested b Register r
Operation: Z ← (HL)b
Operands: b, (HL)
Bit Tested b
Operation: Z ← (IX+d)b
Operands: b, (IX+d)
Operation: Z ← (IY+d)b
Operands: b, (lY+d)
Operation: rb ← 1
Bit b Register r
M Cycles T States4 MHz E.T
Operation: (HL)b ← 1
Operation: (IX+d)b ← 1
Operation: sb ← 0
Op Code: RES
Operands: b, m
Operation: PC ← nn
Op Code: JP
Operands: nn
Operands: cc, nn
Relevant
cc Condition Flag
Operation: PC ← PC + e
Op Code: JR
Operands: e
Location Instruction
Operands: C, e
Operands: NC, e
Operands: Z, e
Operands: NZ, e
Operation: pc ← hL
Operation: pc ← IX
Operands: (IX)
Operation: PC ← IY
Operands: (IY)
Operation: -
Op Code: DJNZ
Op Code: CALL
Location Contents
Operands: cc
Op Code: RETI
Op Code: RETN
Op Code: RST
Operands: p
p t
Op Code: INI
Op Code: INIR
Op Code: IND
Op Code: INDR
Operation: (n) ← A
Operands: (n), A
Operation: (C) ← r
Operands: (C), r
Op Code: OUTI
Op Code: OTIR
Op Code: OUTD
Op Code: OTDR
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Z80.Instruction Set

Z80.Instruction Set

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Published by Ibrahim Farrag

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Published by: Ibrahim Farrag on Jan 07, 2011
Copyright:Attribution Non-commercial

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