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Adriatic Paper RAW-2003

Adriatic Paper RAW-2003

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reconfigurable computing using systemc
reconfigurable computing using systemc

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Published by: prathap13 on Jan 13, 2011
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System-Level Modeling of Dynamically Reconfigurable Hardware with SystemC
Antti Pelkonen
, Kostas Masselos
, Miroslav
VTT Electronics P.O .Box 1100, FIN-90571Oulu, Finland antti.pelkonen@vtt.fi
 INTRACOM SA P.O. Box 68, GR-19002 Peania, Attika, Greecekmas@intracom.gr 
 IMEC  Kapeldreef 75, B 3001 Leuven, Belgiumcupac@imec.be
To cope with the increasing demand for higher computational power and run-time flexibility, dynamicallyre-configurable blocks become an important part inside a system-on-chip realization. Several methods have been proposed to incorporate their reconfiguration aspectsinside the design process. They all lack either an interfaceto commercially available and industrially used tools or are restricted to a single vendor or technologyenvironment. Therefore a methodology is presented for modeling of dynamically re-configurable blocks at the system-level using SystemC 2.0 as modeling language. Thehigh-level model is based on a multiple-context representation of the different functionalities that will bemapped on the re-configurable block during different run-time periods. By specifying the estimated times of context- switching and active-running in the selected functionalitymodes, the methodology allows to do true design spaceexploration at the system-level, without the need to mapthe design first to an actual technology implementation.
1. Introduction
With the rising performance available for System-on-Chip (SoC) designers and simultaneously risingmanufacturing costs, there is a pressing financial reasonsfor adding more flexibility to the SoC designs withoutsacrificing the performance and possible parallelism of ASIC. Reconfigurable technologies [1, 2]are viewed as the solution for getting this flexibility, but the introductionof dynamic reconfiguration (also known as run-timereconfiguration) adds new dimensions to the design spaceof a SoC designer, since the same area can be configuredfor different functions at different times.The cost-efficient design of dynamically reconfigurableSoCs require support from tools and methodologies for allabstraction layers and design phases. So far, there has beena absence of industrially adaptable methodologies andtools for system-level design and especially design spaceexploration. Also the problem with the methodologies presented by the academia is that they can not be adaptedto the used design flows of the industry without substantialmodifications to the re-usable code base. They are alsooften bounded to single implementation technology.A large portion of the SoC designs using dynamicallyreconfigurable hardware are not designed from scratch.The starting point of such designs are often a previousversion of the SoC with some more features (Figure 1a).The goal of the design is to implement all the old featuresand some new ones and implement some parts of theapplication on dynamically reconfigurable hardware(Figure 1b).
SWFunctionalityDMAMEMHW AcceleratorHW AcceleratorDMAMEMHW AcceleratorFunctionalityHW AcceleratorFunctionlityReconfigurableFabric
Figure 1. (a) Typical SoC architecture and (b) themodified architecture using dynamicallyreconfigurable hardware.
This paper presents a system-level modelingmethodology and associated tools capable of doing quick design space exploration and which takes in to account thespecial properties of dynamically reconfigurable hardware.The methodology is based on SystemC, which is rapidly becoming the language of choice for system-level design.This is partly due to the fact that all large EDA vendorssupport or plan to support SystemC in their tools.The rest of the paper is organized as follows: In chapter 2,dynamic reconfiguration is defined and the benefits anddrawbacks of its use are identified. In chapter 3,classes of reconfigurable technologies are presented with caseexamples. Chapter 4 presents a quick overview of relatedresearch and moderns industrially used system-level co-design tools. In chapter 5,the modeling methodology is presented along with description of a co-design flowdeveloped in projects ADRIATIC. In sub-chapter 5.4andin chapter 6,some limitations and the need of further work is identified.
2. Dynamic reconfigurability
Reconfigurable hardware aims at bridging the gap between implementation efficiency and flexibility asshown inFigure 2[3
. This is achieved sincereconfigurable hardware combines the capability for post-fabrication functionality modification (not present inconventional ASICs) with the spatial/parallel computationstyle (not present in instruction set processors).
       F       l     e     x       i       b       i       l       i       t     y
Area/Power Dedicated/DirectMapped Hardware(ASIC)100-1000MOPS/mWEmbeddedReconfigurableLogic/FPGAReconfigurableProcessor/FPGAPotential of 10-100MOPS/mW ?Reconfiguration overhead ?Application SpecificInstruction Set Processor (ASIP)Instruction SetDSP (TI 320CXX)1-10MIPS/mW0.1-1MIPS/mWEmbeddedGeneral PurposeInstruction SetProcessor (LP ARM)Factor of 100-1000Post fabricationprogrammabilitySpatial computationstyleTemporalcomputationstyleLimitedparallelismUnlimitedparallelism
Figure 2 Flexibility versus implementation efficiencytrade-off for different architectural styles.
Reconfigurable architectures can be classified withrespect to the following parameters:a) reconfiguration scheme, b) coupling to a host microprocessor, andc) granularity of processing elements.
 Reconfiguration scheme:
Traditional reconfigurablesystems are
 statically reconfigurable
, which means that thesystem is configured at the start of execution and remainsunchanged for the duration of the application. In order toreconfigure a statically reconfigurable system, the systemhas to be halted while the reconfiguration is in progressand then restarted with the new configuration.
 Dynamically reconfigurable
run-time reconfigurable
)systems, on the other hand, allow reconfiguration andexecution to proceed at the same time. In this waydynamically reconfigurable systems permit the partialreconfiguration of certain logic blocks while others are performing computations.
This refers to the degree of coupling with ahost microprocessor. In a closely coupled systemreconfigurable units are placed on the data path of the processor, acting as execution units. Loosely coupledsystems act as a coprocessor. They are connected to a hostcomputer system through channels or some special- purpose hardware.
Granularity of processing elements:
This refers to thelevels of manipulation of data. In
 architectures, the basic programmed building block consists of a combinatorial network and a few flip-flops.These blocks are connected with a reconfigurableinterconnection network.
architectures are primarily intended for the implementation of word-widthdata path circuits. Medium grained architectures can beconsidered as coarse grained architectures handling smallword-width data.The inclusion of reconfigurable hardware to a givensystem introduces significant advantages both from amarket and from an implementation point of view.Currently equipment manufacturers move more and moretowards solutions that can be upgraded in the field. Thisallows them to introduce first not fully completed productsversions for time-to-market reasons and then extend products’ lifetimes through firmware upgrades. The mainreasons for this are:- Need to conform to multiple or migratinginternational standards- Emerging improvements and enhancements tostandards- Desire to add features and functionality to existingequipmentThe presence of reconfigurable hardware in such asystem allows low cost adaptivity since the samereconfigurable hardware may be shared among algorithmsrequired for different operational conditions.Finally reconfigurable hardware introduces the bugfixing capability for hardware systems in a software-likemanner. In this way costly re-fabrications of VLSIcomponents can be avoided.Although the presence of reconfigurable hardware isadvantageous in many cases significant overheads may bealso introduced. These are mainly related to the timerequired for the reconfiguration and to the power consumed for reconfiguring (a part of) a system. Areaimplications are also introduced (memories storingconfigurations, circuit required to control thereconfiguration procedure). Furthermore existing systemlevel methodologies need to be extended to cover issuesrelated to the presence of reconfigurable hardware. 
3. Reconfigurable technologies
Currently available (re)-configurable technologies can be classified in following major categories:
a) System level FPGAs:
Currently available FPGAsoffer sufficient density and speed to allow a completedesign, from the microprocessor to all of its peripheralfunctions, in a single system-on-a-programmable chip. Anexample of system-level FPGA is the Xilinx Virtext-II Pro product family. Virtex-II Pro based family of FPGAs,embeds from one to four RISC IBM PowerPC processors,using 32-bit CoreConnect on-chip bus
The Virtex-II ProArchitecture features up to 638K logic gates, 4 PowerPCs,16 multi-gigabit transceivers and 3888Kbits BRAM. The
PowerPC 405 RISC core provides over 300 MHz and 420MIPS of performance, while consuming 0.9 mW/MHz of  power. The Virtex-II Pro features 18Kbit block dual-portRAM, and 128-bit single-port or 64-bit dual-portdistributed RAM. The device includes dedicated high-speed multipliers operating at 200 MHz pipelined, whichsupport up to 18-bit signed or up to 17-bit unsignedrepresentations, and they can be cascaded to support bigger numbers. Virtex family is dynamicallyreconfigurable comprising a fine grain architecture withgranularity of 1-bit. The Virtex-II Pro architecturerepresents a typical SRAM based FPGA style device withregular arrays of CLBs surrounded by programmableinput/output blocks.
b) Embedded reconfigurable cores/FPGAs:
 Embedded FPGA approaches are based on the idea of embedding bits of programmable logic into an ASIC inorder to keep it (partly) programmable even after it comesout of the fab. An example of such reconfigurabletechnology is Actel's VariCore.Actel’s VariCore IP blocks are embedded, dynamicallyreprogrammable "soft hardware" cores designed for use inASIC and SoC applications. Varicore is an architectureconsisting of scaleable, configurable and partitionable programmable logic blocks from 2,500 to 40,000 ASICgates for 0.18µ technology. VariCore EPGAs can be partitioned where needed throughout any ASIC or SoCdesign. Up to 73,728 bits of RAM can be available. PEGsare the primary logic blocks of VariCore EPGAsconsisting of 2,500 ASIC gates. These PEG blocks arescaleable and configurable from a 2x1 EPGA of 5,000ASIC gates up to an 8x8 EPGA of 160,000 ASIC gates (amaximum of 40,000 ASICgates in VariCore's 0.18 µmfamily). In addition, the .18µ EPGA family's 4x4 and 4x2members offer eight optional, cascadable RAM moduleswith two aspect ratios of 1k*9 or 512*18. The firstcommercially available VariCore embedded programmablegate array (EPGA) blocks have been designed in 0.18micron CMOS SRAM technology with 1.8V operatingvoltage for clock speeds up to 250 MHz. VariCore programmable logic is supported by the leading siliconfoundries, including UMC, TSMC and CharteredSemiconductor.Some power consumption figures include:- 0.075 µW/Gate/MHz- Typically 240 mW at 100 MHz and 80% utilization
c) Arrays of processing elements:
Arrays of  processing elements usually represents the combination of an instruction set processor (RISC) with reconfigurablefabric of coarse grain elements. MorphoSys [4]is a parallel system-on-chip which combines a RISC processor with an array of coarse-grain reconfigurable cells, withmultiple context words, operating in SIMD fashion. It is primarily targeted for applications with inherent parallelism, high regularity, word-level granularity andcomputation intensive nature.MorphoSys reconfigurable architecture is composed of a control processor, reconfigurable array (RA), data buffer,DMA controller, context memory and instruction/datacache.In addition to typical RISC instructions, TinyRISCcontrol processors ISA is augmented with specificinstructions for controlling DMA and RA. The core processor executes sequential tasks of the application andcontrols data transfers between the programmablehardware and data memory.The reconfigurable array consists of an 8×8 matrix of Reconfigurable Cells (RCs). An important feature of theRC Array is its three-layer interconnection network. Thefirst layer connects the RCs in a two-dimensional mesh,allowing nearest neighbour data interchange. The secondlayer provides complete row and column connectivitywithin an array quadrant. It allows each RC to access datafrom any other RC in its row/column in the same quadrant.The third layer supports inter-quadrant connectivity. TheRC is the basic programmable element in MorphoSys.Each RC comprises: an ALU-Multiplier, a shift unit, inputmultiplexers, a register file with four 16-bit registers andthe context register.The Context Memory stores the configuration programfor the RC Array, the Frame Buffer stores the intermediatedata.The DMA controller performs data transfers betweenthe Frame Buffer and the main memory. It is alsoresponsible for loading contexts into the Context Memory.The TinyRISC core processor uses DMA instructions tospecify the necessary data/context transfer parameters for the DMA controller.MorphoSys is dynamically reconfigurable architecture.While the RC array is executing one of the 16 contexts, theother 16 contexts can be reloaded into the contextmemory.As can be seen, the different categories of dynamicallyreconfigurable technologies have very differentcharacteristics and therefore, a unified model of them atthe system-level is impossibility. One way of achievingaccurate simulation results when doing design spaceexploration at system-level is to parameterise theconfiguration memory transfers at context switch and thedelays associated with the reconfiguration process.
4. Related research and available tools
Since the dynamically reconfigurable systems potentially provide good tradeoff between performanceand flexibility, there has been a lot of research going on inthe field.A good review of reconfigurable computing has been done in [1]. The reconfigurable hardware, associated

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