2. Dynamic reconfigurability
Reconfigurable hardware aims at bridging the gap between implementation efficiency and flexibility asshown inFigure 2[3
. This is achieved sincereconfigurable hardware combines the capability for post-fabrication functionality modification (not present inconventional ASICs) with the spatial/parallel computationstyle (not present in instruction set processors).
F l e x i b i l i t y
Area/Power Dedicated/DirectMapped Hardware(ASIC)100-1000MOPS/mWEmbeddedReconfigurableLogic/FPGAReconfigurableProcessor/FPGAPotential of 10-100MOPS/mW ?Reconfiguration overhead ?Application SpecificInstruction Set Processor (ASIP)Instruction SetDSP (TI 320CXX)1-10MIPS/mW0.1-1MIPS/mWEmbeddedGeneral PurposeInstruction SetProcessor (LP ARM)Factor of 100-1000Post fabricationprogrammabilitySpatial computationstyleTemporalcomputationstyleLimitedparallelismUnlimitedparallelism
Figure 2 Flexibility versus implementation efficiencytrade-off for different architectural styles.
Reconfigurable architectures can be classified withrespect to the following parameters:a) reconfiguration scheme, b) coupling to a host microprocessor, andc) granularity of processing elements.
Traditional reconfigurablesystems are
, which means that thesystem is configured at the start of execution and remainsunchanged for the duration of the application. In order toreconfigure a statically reconfigurable system, the systemhas to be halted while the reconfiguration is in progressand then restarted with the new configuration.
)systems, on the other hand, allow reconfiguration andexecution to proceed at the same time. In this waydynamically reconfigurable systems permit the partialreconfiguration of certain logic blocks while others are performing computations.
This refers to the degree of coupling with ahost microprocessor. In a closely coupled systemreconfigurable units are placed on the data path of the processor, acting as execution units. Loosely coupledsystems act as a coprocessor. They are connected to a hostcomputer system through channels or some special- purpose hardware.
Granularity of processing elements:
This refers to thelevels of manipulation of data. In
architectures, the basic programmed building block consists of a combinatorial network and a few flip-flops.These blocks are connected with a reconfigurableinterconnection network.
architectures are primarily intended for the implementation of word-widthdata path circuits. Medium grained architectures can beconsidered as coarse grained architectures handling smallword-width data.The inclusion of reconfigurable hardware to a givensystem introduces significant advantages both from amarket and from an implementation point of view.Currently equipment manufacturers move more and moretowards solutions that can be upgraded in the field. Thisallows them to introduce first not fully completed productsversions for time-to-market reasons and then extend products’ lifetimes through firmware upgrades. The mainreasons for this are:- Need to conform to multiple or migratinginternational standards- Emerging improvements and enhancements tostandards- Desire to add features and functionality to existingequipmentThe presence of reconfigurable hardware in such asystem allows low cost adaptivity since the samereconfigurable hardware may be shared among algorithmsrequired for different operational conditions.Finally reconfigurable hardware introduces the bugfixing capability for hardware systems in a software-likemanner. In this way costly re-fabrications of VLSIcomponents can be avoided.Although the presence of reconfigurable hardware isadvantageous in many cases significant overheads may bealso introduced. These are mainly related to the timerequired for the reconfiguration and to the power consumed for reconfiguring (a part of) a system. Areaimplications are also introduced (memories storingconfigurations, circuit required to control thereconfiguration procedure). Furthermore existing systemlevel methodologies need to be extended to cover issuesrelated to the presence of reconfigurable hardware.
3. Reconfigurable technologies
Currently available (re)-configurable technologies can be classified in following major categories:
a) System level FPGAs:
Currently available FPGAsoffer sufficient density and speed to allow a completedesign, from the microprocessor to all of its peripheralfunctions, in a single system-on-a-programmable chip. Anexample of system-level FPGA is the Xilinx Virtext-II Pro product family. Virtex-II Pro based family of FPGAs,embeds from one to four RISC IBM PowerPC processors,using 32-bit CoreConnect on-chip bus
The Virtex-II ProArchitecture features up to 638K logic gates, 4 PowerPCs,16 multi-gigabit transceivers and 3888Kbits BRAM. The