PLD Design Flow: FPGA, Verilog
This document describes the step-by-step process to create, simulate, and implement a XilinxFPGA-based design using the Cadence/Orcad design suite for simulation and the Xilinx tools for implementation.
•Xilinx Web Pack FPGA implementation software•Cadence NC-Simulator
•Spartan2E FPGA Development Board (checked out from the instrument room)
Boldface type indicates comments that are particuarly critical to the success of your projectand/or prevents the destruction of your device.What to Do:How To Do It:
Create a Conceptual Design
Draw I/O block diagram of your circuit (i.e. rectanglewith pins sticking out and aname for each pin/signal)Use a piece of paper and pen or pencil to do this!You may need to clarify some details using a manner thatthe design can easily be changed before jumping in withthe computer tools.Draw a diagram of your circuit components andtheir interconnectionsSee above.The diagram will help you visualize the hardware beforewriting the HDL.
Enter Your Design:
Set up design directoryCreate a new folder for your design files.Run the Cadence NC-Sim-ulator softwareRun Programs | Cadence Design Systems | AffirmaDesign and Verification | NCLaunchChange your workingdirectoryFile | Set Design DirectoryChange the design directory to the folder you createdabove(only the first time your run the program) create a cds.libfile