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Published by: Varadha Rajan on Jan 21, 2011
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Synthesis andSimulationDesign Guide
 
8.1i
 
Synthesis and Simulation Design Guide
Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operateon, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished,downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical,photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyrightlaws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes.Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents,copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design.Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes noobligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for theaccuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design.THE DESIGN IS PROVIDED “AS IS” WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION ISWITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION ORADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHEREXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESSFOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS.IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES,INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOUHAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTIONWITH YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THEAMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IFANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLETHE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY.The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail-safe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, orweapons systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-RiskApplications. You represent that use of the Design in such High-Risk Applications is fully at your risk.Copyright © 1995-2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarksof Xilinx, Inc. PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners.
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Synthesis and Simulation Design Guide
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Preface
 About This Guide
This guide provides a general overview of designing Field Programmable Gate Arrays(FPGA devices) with Hardware Description Languages (HDLs). It includes design hintsfor the novice HDL user, as well as for the experienced user who is designing FPGAdevices for the first time.The design examples in this guide were:
created with Verilog and VHSIC Hardware Description Language (VHDL)
compiled with various synthesis tools
targeted for Spartan™-II, Spartan-IIE, Spartan-3, Spartan-3E, Virtex™, Virtex-E,Virtex-II, Virtex-II Pro, Virtex-II Pro X and Virtex-4 devicesXilinx® equally endorses both Verilog and VHDL. VHDL may be more difficult to learnthan Verilog, and usually requires more explanation.This guide does not address certain topics that are important when creating HDL designs,such as the design environment; verification techniques; constraining in the synthesis tool;test considerations; and system verification. For more information, see your synthesis tooldocumentation and design methodology notes.Before using this guide, you should be familiar with the operations that are common to allXilinx software tools.
Guide Contents
This guide contains the following chapters.
Chapter 1,“Introduction,”provides a general overview of designing FieldProgrammable Gate Arrays (FPGA devices) with HDLs. This chapter also includesinstallation requirements and instructions.
Chapter 2,“Understanding High-Density Design Flow,”provides synthesis andXilinx implementation techniques to increase design performance and utilization.
Chapter 3,“General HDL Coding Styles,”includes HDL coding hints and designexamples to help you develop an efficient coding style.
Chapter 4,“Coding Styles for FPGA Devices,”includes coding techniques to help youuse the latest Xilinx FPGA devices.
Chapter 5“Using SmartModels,”describes the special considerations encounteredwhen simulating designs for Virtex-II Pro and Virtex-II Pro X FPGA devices.
Chapter 6,“Simulating Your Design,”describes simulation methods for verifying thefunction and timing of your designs.
Chapter 7,“Equivalency Checking.”Information on equivalency checking is nolonger included in the
Synthesis and Simulation Design Guide
. For information on

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